參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 102/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
S1C88848 TECHNICAL MANUAL
EPSON
25
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Watchdog Timer)
5.2 Watchdog Timer
5.2.1 Configuration of watchdog timer
The S1C88848 is equipped with a watchdog timer
driven by OSC1 as source oscillation. The watchdog
timer must be reset periodically in software, and if
reset of more than 3–4 seconds (when fOSC1 = 32.768
kHz) does not take place, a non-maskable interrupt
signal is generated and output to the CPU.
Figure 5.2.1.1 is a block diagram of the watchdog
timer.
1 Hz
Watchdog timer
reset signal
Non-maskable
interrupt (NMI)
Watchdog
timer
Divider
WDRST
fOSC1
OSC1
oscillation
circuit
Fig. 5.2.1.1 Block diagram of watchdog timer
By running watchdog timer reset during the main
routine of the program, it is possible to detect
program runaway as if watchdog timer processing
had not been applied. Normally, this routine is
integrated at points that are regularly being
processed.
The watchdog timer continues to operate during
HALT and when a HALT state is continuous for
longer than 3–4 seconds, the CPU shifts to excep-
tion processing.
During SLEEP, the watchdog timer is stopped.
5.2.2 Interrupt function
In cases where the watchdog timer is not periodi-
cally reset in software, the watchdog timer outputs
_______
an interrupt signal to the CPU's NMI (level 4) input.
Unmaskable and taking priority over other inter-
rupts, this interrupt triggers the generation of
exception processing. See the "S1C88 Core CPU
_______
Manual" for more details on NMI exception
processing.
This exception processing vector is set at 000004H.
5.2.3 Control of watchdog timer
Table 5.2.3.1 shows the control bits for the watch-
dog timer.
WDRST: 00FF40HD2
Resets the watchdog timer.
When "1" is written: Watchdog timer is reset
When "0" is written: No operation
Reading:
Constantly "0"
By writing "1" to WDRST, the watchdog timer is
reset, after which it is immediately restarted.
Writing "0" will mean no operation.
Since WDRST is for writing only, it is constantly set
to "0" during readout.
5.2.4 Programming notes
(1) The watchdog timer must reset within 3-second
cycles by software.
(2) Do not execute the SLP instruction for 2 msec
_______
after a NMI interrupt has occurred (when fOSC1
is 32.768 kHz).
Table 5.2.3.1 Watchdog timer control bits
Address Bit
Name
00FF40 D7
D6
D5
D4
D3
D2
D1
D0
–
FOUT2
FOUT1
FOUT0
FOUTON
WDRST
TMRST
TMRUN
SR R/W
Function
Comment
–
FOUT frequency selection
FOUT output control
Watchdog timer reset
Clock timer reset
Clock timer Run/Stop control
"0" when being read
Constantly "0" when
being read
10
–
0
–
0
R/W
W
R/W
–
On
Reset
Run
–
Off
No operation
Stop
FOUT2
0
1
FOUT1
0
1
0
1
FOUT0
0
1
0
1
0
1
0
1
Frequency
fOSC1 / 1
fOSC1 / 2
fOSC1 / 4
fOSC1 / 8
fOSC3 / 1
fOSC3 / 2
fOSC3 / 4
fOSC3 / 8
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