參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 117/174頁
文件大小： 1304K
代理商： S1C88848D0A0100
S1C88848 TECHNICAL MANUAL
EPSON
39
5 PERIPHERAL CIRCUITS AND THEIR OPERATIO (Output Ports)
Table 5.5.6.1(b) Output port control bits
SR R/W
Address Bit
Name
Function
Comment
10
00FF30 D7
D6
D5
D4
D3
D2
D1
D0
–
CHSEL
PTOUT
CKSEL1
CKSEL0
–
Constantly "0" when
being read
–
0
R/W
–
16-bit x 1
Timer 1
On
fOSC3
–
8-bit x 2
Timer 0
Off
fOSC1
8/16-bit mode selection (timer 0/1)
TOUT output channel selection
TOUT output control
Prescaler 1 source clock selection
Prescaler 0 source clock selection
MODE160
00FF40 D7
D6
D5
D4
D3
D2
D1
D0
–
FOUT2
FOUT1
FOUT0
FOUTON
WDRST
TMRST
TMRUN
–
FOUT frequency selection
FOUT output control
Watchdog timer reset
Clock timer reset
Clock timer Run/Stop control
"0" when being read
Constantly "0" when
being read
–
0
–
0
R/W
W
R/W
–
On
Reset
Run
–
Off
No operation
Stop
FOUT2
0
1
FOUT1
0
1
0
1
FOUT0
0
1
0
1
0
1
0
1
Frequency
fOSC1 / 1
fOSC1 / 2
fOSC1 / 4
fOSC1 / 8
fOSC3 / 1
fOSC3 / 2
fOSC3 / 4
fOSC3 / 8
00FF44 D7
D6
D5
D4
D3
D2
D1
D0
–
BZSTP
BZSHT
SHTPW
ENRTM
ENRST
ENON
BZON
–
One-shot buzzer forcibly stop
One-shot buzzer trigger/status
One-shot buzzer duration width selection
Envelope attenuation time
Envelope reset
Envelope On/Off control
Buzzer output control
Constantly "0" when
being read
"0" when being read
*1
–
0
–
0
W
R/W
W
R/W
–
Forcibly stop
Busy
Trigger
125 msec
1 sec
Reset
On
–
No operation
Ready
No operation
31.25 msec
0.5 sec
No operation
Off
R
W
*1 Reset to "0" during one-shot output.
■ High impedance control
HZR26, HZR27: 00FF71HD6, D7
HZR34: 00FF72HD4
HZR50, HZR51: 00FF70HD6, D7
Sets the output terminals to a high impedance state.
When "1" is written: High impedance
When "0" is written: Complementary
Reading:
Valid
HZRxx is the high impedance control register
which correspond to the Rxx output port terminal.
When "1" is set to the HZRxx register, the corre-
sponding output port terminal becomes high
impedance state and when "0" is set, it becomes
complementary output.
This control is effective even if the port is set as a
special output port.
At initial reset, this register is set to "0"
(complementary).
HZR20–HZR23: 00FF71HD0–D3
HZR30–HZR33: 00FF72HD0–D3
HZR35–HZR37: 00FF72HD5–D7
Sets the SEG40–SEG50 terminals (configured for
DC output) to a high impedance state.
When "1" is written: High impedance
When "0" is written: Complementary
Reading:
Valid
HZR20–23, HZR30–33 and HZR35–37 are the high
impedance control registers that correspond to the
SEG50–47, SEG46–43 and SEG42–40 terminals,
respectively, and are effective only when the SEG
terminal is configured for DC output by mask
option. HZRxx for the terminal configured as LCD
segment output can be used as a general-purpose
register that does not affect the output.
At initial reset, this register is set to "0"
(complementary).
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