參數(shù)資料
型號(hào)： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁(yè)數(shù)： 39/174頁(yè)
文件大小： 1304K
代理商： S1C88848D0A0100
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S1C88848 TECHNICAL MANUAL
EPSON
125
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
■ HALT status
By executing the program's HALT instruction, the
S1C88848 shifts to the HALT status.
Since CPU operation stops in the HALT status,
power consumption can be reduced with only
peripheral circuit operation.
Cancellation of the HALT status is done by initial
reset or an optional interrupt request, and the CPU
restarts program execution from an exception
processing routine.
See the "S1C88 Core CPU Manual" for the HALT
status and reactivation sequence.
■ SLEEP status
By executing the program's SLP instruction, the
S1C88848 shifts to the SLEEP status.
Since the operation of the CPU and peripheral circuits
stop completely in the SLEEP status, power consump-
tion can be reduced even more than in the HALT status.
Cancellation of the SLEEP status is done by initial
reset or an input interrupt from the input port. The
CPU reactivates after waiting 128/fOSC1 seconds of
oscillation stabilization time. At this time, the CPU
restarts program execution from an exception
processing routine (input interrupt routine).
Note: Since oscillation is unstable for a short time
after reactivation from the SLEEP status, the
wait time is not always 3.9 msec even when
using the 32.768 kHz crystal oscillator for
the OSC1 oscillation circuit.
5.15.1 Interrupt generation conditions
The interrupt factor flags that indicate the generation
of their respective interrupt factors are provided for
the previously indicated 8 systems and 18 types of
interrupts and they will be set to "1" by the genera-
tion of a factor.
In addition, interrupt enable registers with a 1 to 1
correspondence to each of the interrupt factor flags
are provided. An interrupt is enabled when "1" is
written and interrupt is disabled when "0" is written.
The CPU manages the enable/disable of interrupt
requests at the interrupt priority level. An interrupt
priority register that sets the priority level is
provided for each of the interrupts of the 8 systems
and the CPU accepts only interrupts above the level
that has been indicated with the interrupt flags (I0
and I1).
Consequently, the following three conditions are
necessary for the CPU to accept the interrupt.
(1) The interrupt factor flag has been set to "1" by
generation of an interrupt factor.
(2) The interrupt enable register corresponding to
the above has been set to "1".
(3) The interrupt priority register corresponding to
the above has been set to a priority level higher
than the interrupt flag (I0 and I1) setting.
The CPU initially samples the interrupt for the first
op-code fetch cycle of each instruction. Thereupon,
the CPU shifts to the exception processing when the
above mentioned conditions have been established.
See the "S1C88 Core CPU Manual" for the exception
processing sequence.
5.15.2 Interrupt factor flag
Table 5.15.2.1 shows the correspondence between
the factors generating an interrupt and the inter-
rupt factor flags.
The corresponding interrupt factor flags are set to
"1" by generation of the respective interrupt factors.
The corresponding interrupt factor can be con-
firmed by reading the flags through software.
Table 5.15.2.1 Interrupt factors
FPT1
FPT0
FPT3
FPT2
FK1
FK0H
FK0L
FSERR
FSREC
FSTRA
FSW100
FSW10
FSW1
FTM32
FTM8
FTM2
FTM1
FREM
Programmable timer 1 underflow
Programmable timer 0 underflow
Programmable timer 3 underflow
Programmable timer 2 underflow
Non matching of the K10–K11 inputs and the input comparison registers KCP10–KCP11
Non matching of the K04–K07 inputs and the input comparison registers KCP04–KCP07
Non matching of the K00–K03 inputs and the input comparison registers KCP00–KCP03
Serial interface receiving error (in asynchronous mode)
Serial interface receiving completion
Serial interface transmitting completion
Falling edge of the stopwatch timer 100 Hz signal
Falling edge of the stopwatch timer 10 Hz signal
Falling edge of the stopwatch timer 1 Hz signal
Rising edge of the clock timer 32 Hz signal
Rising edge of the clock timer 8 Hz signal
Rising edge of the clock timer 2 Hz signal
Rising edge of the clock timer 1 Hz signal
Remote controller output control
Interrupt factor
Interrupt factor flag
(00FF25 D7)
(00FF25 D6)
(00FF27 D7)
(00FF27 D6)
(00FF25 D5)
(00FF25 D4)
(00FF25 D3)
(00FF25 D2)
(00FF25 D1)
(00FF25 D0)
(00FF24 D6)
(00FF24 D5)
(00FF24 D4)
(00FF24 D3)
(00FF24 D2)
(00FF24 D1)
(00FF24 D0)
(00FF27 D5)
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