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參數(shù)資料
| 型號(hào)： | S1C88848D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192 |
| 封裝： | DIE-192 |
| 文件頁(yè)數(shù)： | 74/174頁(yè) |
| 文件大?。?/td> | 1304K |
| 代理商： | S1C88848D0A0100 |
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S1C88848 TECHNICAL MANUAL
EPSON
157
APPENDIX A S5U1C88000P1&S5U1C88816P2 MANUAL (Peripheral Circuit Board for S1C88848)
(5) OSC1 H control
This control is used for coarse adjustment of
the OSC1 CR oscillation frequency.
(6) OSC1 L control
This control is used for fine adjustment of the
OSC1 CR oscillation frequency.
(7) OSC3 H control
This control is used for coarse adjustment of
the OSC3 CR oscillation frequency.
(8) OSC3 L control
This control is used for fine adjustment of the
OSC3 CR oscillation frequency.
(9) RESET switch
This switch initializes the internal circuits of
this board and feeds a reset signal to the ICE.
(10) LEDs 1 to 3 (Reserved)
Unused.
(11) LED 4 (CLKCHG)
Indicates the CPU operating clock.
Lit:
OSC3 (CLKCHG register = "1")
Not lit: OSC1 (CLKCHG register = "0")
(12) LED 5 (OSCC)
Indicates the OSC3 oscillation status.
Lit:
OSC3 oscillation is on
(OSCC register = "1")
Not lit: OSC3 oscillation is off
(OSCC register = "0")
(13) LED 6 (SVDON)
Indicates the SVD circuit status.
Lit:
SVD circuit is on
(SVDON register = "1")
Not lit: SVD circuit is off
(SVDON register = "0")
(14) LED 7 (LCDC)
Indicates the LCD circuit status.
Lit:
LCD circuit is on
(LCDC register = Not "00")
Not lit: LCD circuit is off
(LCDC register = "00")
(15) LED 8 (Reserved)
Unused.
(16) LED 9 (HALT/SLEEP)
Indicates the CPU status.
Lit:
HALT or SLEEP
Not lit: RUN
(17) LED 10 (OSC1 operating clock)
The OSC1 operating clock is connected to this
LED. The corresponding monitor pin (pin 10)
can be used to check the OSC1 clock frequency.
(18) LED 11 (OSC3 operating clock)
The OSC3 operating clock is connected to this
LED. The corresponding monitor pin (pin 11)
can be used to check the OSC3 clock frequency.
(19) LEDs 12 to 15 (Reserved)
Unused.
(20) LED 16 (FPGA configuration)
If the FPGA on the S5U1C88000P1 includes
circuit data, this LED lights when the power is
turned on. If this LED does not light at power-
up, a circuit data must be written to the FPGA
before debugging can be started (turn the
power on again after writing data).
(21) LED signal monitor connector
This connector provides the signals that drive the
LEDs shown above for monitoring. The signals
listed below are output from the connector pins.
The signal level is high when the LED is lit and is
low when the LED is not lit.
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
Fig. A.1.3 LED signal monitor connector
Pin 4: LED 4 (CPU operating clock)
Pin 5: LED 5 (OSC3 oscillation status)
Pin 6: LED 6 (SVD circuit status)
Pin 7: LED 7 (LCD circuit status)
Pin 9: LED 9 (HALT/SLEEP, RUN status)
Pin 10: OSC1 operating clock
Pin 11: OSC3 operating clock
Pin 18: OSC1 CR oscillation frequency monitor pin
Pin 19: OSC3 CR oscillation frequency monitor pin
Pins 1 to 3, 8, 12 to 17 and 20 are not used.
The OSC3 CR oscillation clock is connected to
pins 18 and 19. (The CR oscillation circuit on
this board always operates even if crystal
oscillation is selected by mask option and
regardless of the OSCC register status.) These
pins can be used to monitor CR oscillation
when adjusting the oscillation frequency.
(22) I/O #1, I/O #2, I/O #3 connectors
These are the connectors for connecting the I/
O and LCD. The I/O cables (80-pin/40-pin
× 2
flat type, 60-pin/30-pin
× 2 flat type) are used
to connect to the target system.
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