參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 111/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
S1C88848 TECHNICAL MANUAL
EPSON
33
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Input Ports)
Table 5.4.4.1(b) Input port control bits
K00D–K07D: 00FF54H
K10D, K11D: 00FF55HD0, D1
Input data of input port terminal Kxx can be read out.
When "1" is read:
HIGH level
When "0" is read:
LOW level
Writing:
Invalid
The terminal voltage of each of the input port K00–
K07, K10 and K11 can be directly read out as either
a "1" for HIGH (VDD) level or a "0" for LOW (VSS)
level.
This bit is exclusively for readout and are not
usable for write operations.
SIK00–SIK07: 00FF50H
SIK10, SIK11: 00FF51HD0, D1
Sets the interrupt generation condition (interrupt
permission/prohibition) for input port terminals
K00–K07, K10 and K11.
When "1" is written: Interrupt permitted
When "0" is written: Interrupt prohibited
Reading:
Valid
SIKxx is the interrupt selection register which
correspond to the input port Kxx. A "1" setting
permits interrupt in that input port and a "0"
prohibits it. Changes of state in an input terminal in
which interrupt is prohibited, will not influence
interrupt generation.
At initial reset, this register is set to "0" (interrupt
prohibited).
SR R/W
Address Bit
Name
Function
Comment
10
00FF20 D7
D6
D5
D4
D3
D2
D1
D0
PK01
PK00
PSIF1
PSIF0
PSW1
PSW0
PTM1
PTM0
0
R/W
PK01
PSIF1
PSW1
PTM1
1
0
PK00
PSIF0
PSW0
PTM0
1
0
1
0
K00–K07 interrupt priority register
Serial interface interrupt priority register
Stopwatch timer interrupt priority register
Clock timer interrupt priority register
Priority
level
Level 3
Level 2
Level 1
Level 0
00FF21 D7
D6
D5
D4
D3
D2
D1
D0
PREM1
PREM0
PPT3
PPT2
PPT1
PPT0
PK11
PK10
0
R/W
PREM1
PPT3
PPT1
PK11
1
0
PREM0
PPT2
PPT0
PK10
1
0
1
0
REM carrier interrupt priority register
Programmable timer 2–3 interrupt
priority register
Programmable timer 0–1 interrupt
priority register
K10–K11 interrupt priority register
Priority
level
Level 3
Level 2
Level 1
Level 0
D7
D6
D5
D4
D3
D2
D1
D0
00FF23
EPT1
EPT0
EK1
EK0H
EK0L
ESERR
ESREC
ESTRA
0
R/W
Programmable timer 1 interrupt enable register
Programmable timer 0 interrupt enable register
K10–K11 interrupt enable register
K04–K07 interrupt enable register
K00–K03 interrupt enable register
Serial I/F (error) interrupt enable register
Serial I/F (receiving) interrupt enable register
Serial I/F (transmitting) interrupt enable register
Interrupt
enable
Interrupt
disable
00FF25 D7
D6
D5
D4
D3
D2
D1
D0
FPT1
FPT0
FK1
FK0H
FK0L
FSERR
FSREC
FSTRA
Programmable timer 1 interrupt factor flag
Programmable timer 0 interrupt factor flag
K10–K11 interrupt factor flag
K04–K07 interrupt factor flag
K00–K03 interrupt factor flag
Serial I/F (error) interrupt factor flag
Serial I/F (receiving) interrupt factor flag
Serial I/F (transmitting) interrupt factor flag
(R)
Interrupt
factor is
generated
(W)
Reset
(R)
No interrupt
factor is
generated
(W)
No operation
0
R/W
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