參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 54/174頁
文件大小： 1304K
代理商： S1C88848D0A0100
S1C88848 TECHNICAL MANUAL
EPSON
139
7 ELECTRICAL CHARACTERISTICS
■ Serial interface
Clock synchronous master mode
Item
Symbol
Min.
Typ.
Max.
Unit
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
tsmd
tsms
tsmh
ns
Note
250
100
Condition: VDD = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 70
°C, VIH1 = 0.8VDD, VIL1 = 0.2VDD, VOH = 0.8VDD, VOL = 0.2VDD
Clock synchronous slave mode
Item
Symbol
Min.
Typ.
Max.
Unit
Transmitting data output delay time
Receiving data input set-up time
Receiving data input hold time
tssd
tsss
tssh
ns
Note
100
250
Condition: VDD = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 70
°C, VIH1 = 0.8VDD, VIL1 = 0.2VDD, VOH = 0.8VDD, VOL = 0.2VDD
Asynchronous system
Min.
Typ.
Max.
tsa1
tsa2
s
1
2
Note) 1
2
Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating.
(Time as far as AC is excluded.)
Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again
after a start bit has been detected and the internal sampling clock has started.
When a HIGH level is detected, the start bit detection circuit is reset and goes into a wait status until the next start bit.
(Time as far as AC is excluded.)
0
9
t/16
10
t/16
Item
Symbol
Unit
Start bit detection error time
Erroneous start bit detection range time
Note
Condition: VDD = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 70
°C
SCLK OUT
SOUT
SIN
VOH
VOL
tsms
tsmh
tsmd
VIH1
VIL1
VOL
SCLK IN
SOUT
SIN
VIH1
VOH
VOL
tsss
tssh
tssd
VIH1
VIL1
tsa1
t
tsa2
SIN
Start bit
Sampling
clock
Erroneous
start bit
detection signal
Stop bit
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