參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 152/174頁
文件大小： 1304K
代理商： S1C88848D0A0100
S1C88848 TECHNICAL MANUAL
EPSON
71
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Stopwatch Timer)
SWD0–SWD7: 00FF43H
The stopwatch timer data can be read out.
Higher and lower nibbles and BCD digit corre-
spondence are as follows:
SWD0–SWD3:
BCD (1/100sec)
SWD4–SWD7:
BCD (1/10sec)
Since SWD0–SWD7 are exclusively for reading, the
write operation is invalid.
At initial reset, the timer data is set to "00H".
SWRST: 00FF42HD1
Resets the stopwatch timer.
When "1" is written: Stopwatch timer reset
When "0" is written: No operation
Reading:
Always "0"
The stopwatch timer is reset by writing "1" to the
SWRST. When the stopwatch timer is reset in the
RUN status, it restarts immediately after resetting.
In the case of the STOP status, the reset data "00H"
is maintained.
No operation results when "0" is written to the
SWRST.
Since the SWRST is exclusively for writing, it
always becomes "0" during reading.
SWRUN: 00FF42HD0
Controls RUN/STOP of the stopwatch timer.
When "1" is written: RUN
When "0" is written: STOP
Reading:
Valid
The stopwatch timer starts up-counting by writing
"1" to the SWRUN and stops by writing "0".
In the STOP status, the timer data is maintained
until it is reset or set in the next RUN status. Also,
when the STOP status changes to the RUN status,
the data that was maintained can be used for
resuming the count.
At initial reset, the SWRUN is set at "0" (STOP).
PSW0, PSW1: 00FF20HD2, D3
Sets the priority level of the stopwatch timer
interrupt.
The two bits PSW0 and PSW1 are the interrupt
priority register corresponding to the stopwatch
timer interrupt. Table 5.9.4.2 shows the interrupt
priority level which can be set by this register.
Table 5.9.4.2 Interrupt priority level settings
PSW1
PSW0
Interrupt priority level
1
0
1
0
1
0
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
At initial reset, this register is set to "0" (level 0).
ESW1, ESW10, ESW100: 00FF22HD4, D5, D6
Enables or disables the generation of an interrupt
for the CPU.
When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
Reading:
Valid
The ESW1, ESW10 and ESW100 are interrupt
enable registers that respectively correspond to the
interrupt factors for 1 Hz, 10 Hz and 100 Hz.
Interrupts set to "1" are enabled and interrupts set
to "0" are disabled.
At initial reset, this register is set to "0" (interrupt
disabled).
FSW1, FSW10, FSW100: 00FF24HD4, D5, D6
Indicates the stopwatch timer interrupt generation
status.
When "1" is read:
Interrupt factor present
When "0" is read:
Interrupt factor not present
When "1" is written: Resets factor flag
When "0" is written: Invalid
The FSW1, FSW10 and FSW100 are interrupt factor
flags that respectively correspond to the interrupts
for 1 Hz, 10 Hz and 100 Hz and are set to "1" in
synchronization with the falling edge of each signal.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
At initial reset, this flag is reset to "0".
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