參數(shù)資料
型號(hào)： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 158/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
76
EPSON
S1C88848 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
5.10.4 Timer mode
The timer mode counts down using the prescaler
output as an input clock. In this mode, the pro-
grammable timer operates as a timer that obtains
fixed cycles using the OSC1 or OSC3 oscillation
circuit as a clock source.
See "5.10.2 Count operation and basic mode setting"
for basic operation and control, and "5.10.3 Setting
input clock" for the clock source and setting of the
prescaler.
5.10.5 Event counter mode
Timer 0 includes an even counter function that
counts by inputting an external clock (EVIN0) to
input port K10. Also timer 2 has an event counter
function that uses the K11 input port terminal
(EVIN2). This function is selected by writing "1" to
the timer 0 (timer 2) counter mode selection register
EVCNT0 (EVCNT2).
When the event counter mode is selected, timer 0
(timer 2) operates as an event counter and timer 1
(timer 3) operates as a normal timer in 8-bit mode.
In the 16-bit mode, timers 0 and 1 (timers 2 and 3)
operate as 1 channel 16-bit event counter. In the
event counter mode, since the timer 0 (timer 2) is
clocked externally, the setting of the registers PSC0
(PSC2) become invalid.
Count down timing can be controlled by either the
falling edge or rising edge selected by the timer 0
(timer 2) pulse polarity selection register PLPOL0
(PLPOL2). When "0" is written to the register
PLPOL0 (PLPOL2), the falling edge is selected, and
when "1" is written, the rising edge is selected. The
timing is shown in Figure 5.10.5.1.
EVIN0 input (K10)
Count data
n
n-1
n-2
n-3
n-4
n-5
n-6
PLPOL0
EVCNT0
01
1
PRUN0
Fig. 5.10.5.1 Timing chart for event counter mode (timer 0)
The event counter also includes a noise rejecter to
eliminate noise such as chattering for the external
clock (EVIN0, EVIN2). This function is selected by
writing "1" to the timer 0 (timer 2) function
selection register FCSEL0 (FCSEL2).
For a reliable count when "with noise rejecter" is
selected, you must allow 0.98 msec or more pulse
width for both LOW and HIGH levels. (The noise
rejecter allows clocking counter at the second
falling edge of the internal 2,048 Hz signal after
changing the input level of the K10 or K11 input
port terminal. Consequently, the pulse width that
can reliably be rejected is 0.48 msec.)
Figure 5.10.5.2 shows the count down timing with
the noise rejecter selected.
Input clock
to counter
Count data
n
n-1
n-2
n-3
EVIN0 input (K10)
2,048 Hz
When "0" is set into register PLPOL0.
Fig. 5.10.5.2 Count down timing with noise rejecter (timer 0)
The event counter mode is the same as the timer
mode except that the clock is external (EVIN0,
EVIN2).
See "5.10.2 Count operation and setting basic mode"
for the basic operation and control.
5.10.6 Pulse width measurement timer mode
Timer 0 includes a pulse width measurement
function that measures the width of the input signal
(EVIN0) to the K10 input port terminal. Also timer
2 has a pulse width measurement function that uses
the K11 input port terminal (EVIN2). This function
is selected by writing "1" to the timer function
selection register FCSEL0 (FCSEL2) when in the
timer mode (EVCNT0 = "0" in timer 0, EVCNT2 =
"0" in timer 2).
When the pulse width measurement mode is
selected, timer 0 (timer 2) operates as an pulse
width measurement and timer 1 (timer 3) operates
as a normal timer in 8-bit mode. In the 16-bit mode,
timers 0 and 1 (timers 2 and 3) operate as 1 channel
16-bit pulse width measurement.
The level of the input signal (EVIN0, EVIN2) for
measurement can be changed either a LOW or
HIGH level by the timer 0 (timer 2) pulse polarity
selection register PLPOL0 (PLPOL2). When "0" is
written to register PLPOL0 (PLPOL2), a LOW level
width is measured and when "1" is written, a HIGH
level width is measured. The timing is shown in
Figure 5.10.6.1.
The pulse width measurement timer mode is the
same as the timer mode except that the input clock
is controlled by the level of the signal (EVIN0 or
EVIN2) input to the K10 or K11 input port terminal.
See "5.10.2 Count operation and setting basic mode"
for the basic operation and control.
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