參數(shù)資料
型號(hào)： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 129/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
50
EPSON
S1C88848 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
■ Data receive procedure
The control procedure and operation during
receiving is as follows.
(1) Write "0" in the receive enable register RXEN
and transmit enable register TXEN to reset the
serial interface.
(2) Write "1" in the receive enable register RXEN to
set into the receiving enable status.
(3) In case of the master mode, confirm the transmit
ready status on the slave side (external serial
input/output device), if necessary. Wait until it
reaches the transmit ready status.
(4) Write "1" in the receive control bit RXTRG and
start receiving.
In the master mode, this control causes the
synchronous clock to change to enable and is
provided to the shift register for receiving and
_________
output from the SCLK terminal.
In the slave mode, it waits for the synchronous
_________
clock to be input from the SCLK terminal. The
received data input from the SIN terminal is
successively incorporated into the shift register
in synchronization with the rising edge of the
synchronous clock.
At the point where the data of the 8th bit has
been incorporated at the final (8th) rising edge
of the synchronous clock, the content of the shift
register is sent to the received data buffer and
the receiving complete interrupt factor flag
FSREC is set to "1". When interrupt has been
enabled, a receiving complete interrupt is
generated at this point.
(5) Read the received data from TRXD0–TRXD7
using receiving complete interrupt.
(6) Repeat steps (3) to (5) for the number of bytes of
receiving data, and then set the receive disable
status by writing "0" to the receive enable
register RXEN, when the receiving is com-
pleted.
Data receiving
End
RXEN
← 0, TXEN ← 0
No
Yes
Receiving complete ?
Received data reading
from TRXD0–TRXD7
No
Yes
FSREC = 1 ?
RXEN
← 0
RXTRG
← 1
RXEN
← 1
No
Yes
Transmitter ready ?
In case of master mode
Fig. 5.7.6.3 Receiving procedure in clock synchronous mode
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