參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 169/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
86
EPSON
S1C88848 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
FPT0: 00FF25HD6
FPT1: 00FF25HD7
FPT2: 00FF27HD6
FPT3: 00FF27HD7
Indicates the programmable timer interrupt
generation status.
When "1" is read:
Interrupt factor present
When "0" is read:
Interrupt factor not present
When "1" is written: Resets factor flag
When "0" is written: Invalid
FPTx is the interrupt factor flag that corresponds to
the interrupt for timer x and are set to "1" in
synchronization with the underflow of the counter.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
When the 16-bit mode is selected, the interrupt
factor flag FPT0 or FPT2 is not set to "1" and a timer
0 or timer 2 interrupt cannot be generated. (In the
16-bit mode, the interrupt factor flag FPT1 or FPT3
is set to "1" by an underflow of the 16-bit counter.)
At initial reset, this flag is reset to "0".
5.10.11 Programming notes
(1) The programmable timer is actually made to
RUN/STOP in synchronization with the falling
edge of the input clock after writing to the
PRUNx register. Consequently, when "0" is
written to the PRUNx, the timer stops when the
counter is decremented "1". The PRUNx
maintains "1" for reading until the timer actually
stops.
Figure 5.10.11.1 shows the timing chart of the
RUN/STOP control.
PRUNx (WR)
PTDx
42H
41H 40H 3FH 3EH
3DH
PRUNx (RD)
Input clock
Fig. 5.10.11.1 Timing chart of RUN/STOP control
The event counter mode is excluded from the
above note.
(2) The SLP instruction is executed when the
programmable timer is in the RUN status
(PRUNx = "1"). The programmable timer
operation will become unstable when returning
from SLEEP status. Therefore, when shifting to
SLEEP status, set the clock timer to STOP status
(PRUNx = "0") prior to executing the SLP
instruction.
In the same way, disable the TOUT signal
output (PTOUT = "0") to avoid an unstable clock
output to the R27 (R26) output port terminal.
(3) Since the TOUT signal is generated asynchro-
nously from the register PTOUT, when the
signal is turned ON or OFF by the register
setting, a hazard of a 1/2 cycle or less is
generated.
(4) When the OSC3 oscillation circuit is made the
clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable
timer.
From the time the OSC3 oscillation circuit is
turning ON until oscillation stabilizes, an
interval of several 100 sec to several 10 msec is
necessary. Consequently, you should allow an
adequate waiting time after turning the OSC3
oscillation circuit ON before starting the count
of the programmable timer. (The oscillation
start time will vary somewhat depending on the
oscillator and on external parts. Refer to the
oscillation start time example indicated in
Chapter 7, "ELECTRICAL CHARACTERIS-
TICS".)
At initial reset, OSC3 oscillation circuit is set to
ON status.
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