參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 79/174頁
文件大小： 1304K
代理商： S1C88848D0A0100
S1C88848 TECHNICAL MANUAL
EPSON
9
3 CPU AND MEMORY CONFIGURATION
3 CPU AND MEMORY CONFIGURATION
In this section, we will explain the CPU and memory configuration.
3.1 CPU
The S1C88848 utilize the S1C88 8-bit core CPU
whose resistor configuration, command set, etc. are
virtually identical to other units in the family of
processors incorporating the S1C88.
See the "S1C88 Core CPU Manual" for the S1C88.
The S1C88848 supports Model 3/minimum mode
of the S1C88 CPU which allows accessing of the
internal memory mapped within the physical space
from 000000H to 00FFFFH.
3.2 Internal Memory
The S1C88848 is equipped with internal ROM and
RAM as shown in Figure 3.2.1.
00FFFFH
00FF00H
00FD42H
00F800H
00F7FFH
00F600H
00F5FFH
00F000H
00EFFFH
00C000H
00BFFFH
000000H
I/O memory
Display memory
Unused area
RAM
(1.5K bytes)
Unused area
ROM
(48K bytes)
Fig. 3.2.1 Internal memory map
3.2.1 ROM
The internal ROM capacity is shown below.
Capacity: 48K bytes
Address: 000000H to 00BFFFH
3.2.2 RAM
The internal RAM capacity is shown below.
Capacity: 1.5K bytes
Address: 00F000H to 00F5FFH
3.2.3 I/O memory
A memory mapped I/O method is employed in the
S1C88848 for interfacing with internal peripheral
circuit. Peripheral circuit control bits and data
register are arranged in data memory space.
Control and data exchange are conducted via
normal memory access. The I/O memory is
arranged from address 00FF00H to address
00FFFFH. See Section 5.1, "I/O Memory Map", for
details of the I/O memory.
3.2.4 Display memory
The S1C88848 is equipped with an internal display
memory which stores a display data for LCD
driver.
The display memory is arranged from address
00F800H to address 00FD42H (including the
unused area). See Section 5.11, "LCD Controller",
for details of the display memory.
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