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參數(shù)資料
| 型號(hào)： | S1C88848D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192 |
| 封裝： | DIE-192 |
| 文件頁(yè)數(shù)： | 118/174頁(yè) |
| 文件大?。?/td> | 1304K |
| 代理商： | S1C88848D0A0100 |
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40
EPSON
S1C88848 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports)
■ DC output control
R26D, R27D: 00FF75HD6, D7
R34D: 00FF76HD4
R50D, R51D: 00FF78HD0, D1
Sets the data output from the output port terminal
Rxx.
When "1" is written: HIGH level output
When "0" is written: LOW level output
Reading:
Valid
RxxD is the data register for the Rxx output port.
When "1" is set to the register, the corresponding
output port terminal goes HIGH (VDD), and when
"0" is set, it goes LOW (VSS).
At initial reset, R50D is set to "0" (LOW level
output). The other registers are set to "1" (HIGH
level output).
When R26 and/or R51 are set to the special outputs
by mask option, R26D and/or R51D can be used as
general-purpose registers that do not affect the
output status.
R20D–R23D: 00FF75HD0–D3
R30D–R33D: 00FF76HD0–D3
R35D–R37D: 00FF76HD5–D7
Sets data to be output from the SEG40–SEG50
terminals (configured for DC output).
When "1" is written: HIGH level output
When "0" is written: LOW level output
Reading:
Valid
R20D–23D, R30D–33D and R35D–37D are the data
registers that correspond to the SEG50–47, SEG46–
43 and SEG42–40 terminals, respectively, and are
effective only when the SEG terminal is configured
for DC output by mask option. RxxD for the
terminal configured as LCD segment output can be
used as a general-purpose register that does not
affect the output.
At initial reset, this register is set to "1" (HIGH level
output).
■ Special output control
Note: Refer to Section 5.13, "Remote Controller",
for the control registers used for REM
output.
PTOUT: 00FF30HD2
Controls the TOUT (programmable timer output
clock) signal output.
When "1" is written: TOUT signal output ON
When "0" is written: TOUT signal output OFF
Reading:
Valid
PTOUT is the output control register for TOUT
signal. When "1" is set to the register, the TOUT
_________
(TOUT) signal is output from the output port
terminal R27 (R26). When "0" is set, the R27 goes
HIGH (VDD) and the R26 goes LOW (VSS).
To output the TOUT signal, "1" must always be set
for the data register R27D. The data register R26D
_________
does not affect the TOUT output.
At initial reset, PTOUT is set to "0" (output OFF).
_________
The TOUT signal can be output from R26 only
when the function is selected by mask option.
FOUTON: 00FF40HD3
Controls the FOUT (fOSC1/fOSC3 dividing clock)
signal output.
When "1" is written: FOUT signal output
When "0" is written: HIGH level (DC) output
Reading:
Valid
FOUTON is the output control register for FOUT
signal. When "1" is set, the FOUT signal is output
from the output port terminal R34 and when "0" is
set, HIGH (VDD) level is output. At this time, "1"
must always be set for the data register R34D.
At initial reset, FOUTON is set to "0" (HIGH level
output).
FOUT0, FOUT1, FOUT2: 00FF40HD4, D5, D6
FOUT signal frequency is set as shown in Table
5.5.6.2.
Table 5.5.6.2 FOUT frequency settings
FOUT2
FOUT frequency
0
1
fOSC1 / 1
fOSC1 / 2
fOSC1 / 4
fOSC1 / 8
fOSC3 / 1
fOSC3 / 2
fOSC3 / 4
fOSC3 / 8
FOUT1
0
1
0
1
FOUT0
0
1
0
1
0
1
0
1
fOSC1:
fOSC3:
OSC1 oscillation frequency
OSC3 oscillation frequency
At initial reset, this register is set to "0" (fOSC1/1).
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