參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 30/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
S1C88848 TECHNICAL MANUAL
EPSON
117
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Remote Controller)
The
τ waveform is counted at every rising edge.
When the count becomes the number set in RIC, the
interrupt factor flag FREM is set to "1" and an
interrupt occurs in synchronization with that riging
edge.
Set the next carrier output width and the interrupt
timing using this interrupt.
The REM interrupt can be disabled through the
interrupt enable register EREM. However,
regardless of the setting of EREM, FREM is set to
"1" when the counting of the interrupt
τ cycles are
completed.
FREM is reset to "0" by writing "1".
In addition, a priority level of the REM interrupt for
the CPU can be optionally set at levels 0 to 3 by the
interrupt priority registers PREM0 and PREM1.
For details on the above mentioned interrupt
control register and the operation following
generation of an interrupt, see "5.15 Interrupt and
Standby Status".
The exception processing vector addresses for the
REM interrupt factor is set to 000024H.
Figure 5.13.5.6 shows the configuration of the REM
interrupt circuit.
Data written to RIC is maintained while the REM
circuit is ON until the next data is written.
However, the counting of
τ waveform starts using
the write signal for RIC the same as ROUT, so this
register data is valid only one time after writing.
Consequently, data must be written every time
even when generating the next interrupt in the
same cycle count.
The RIC register is undefined at initial reset.
However, the counting of
τ cycles is not performed
until RIC is written after that.
Notes: Once data has been written in RIC, avoid
writing other data into the register before a
REM interrupt occurs (which would
otherwise cause an invalid interrupt).
The values allowed for RIC are 0 to 0EH.
Data
bus
Interrupt
request
Interrupt count
completion
Address
Interrupt factor
flag FREM
Address
Interrupt enable
register EREM
Interrupt priority
level judgment
circuit
Address
Interrupt priority
register PREM0, PREM1
Fig. 5.13.5.6 Configuration of the REM interrupt circuit
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