參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 36/174頁
文件大小： 1304K
代理商： S1C88848D0A0100
122
EPSON
S1C88848 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit)
5.14 Supply Voltage Detection
(SVD) Circuit
5.14.1 Configuration of SVD circuit
The S1C88848 has a built-in SVD (supply voltage
detection) circuit, so that the software can find
when the source voltage lowers. Turning the SVD
circuit ON/OFF and the SVD criteria voltage
setting can be done with software.
Figure 5.14.1.1 shows the configuration of the SVD
circuit.
5.14.2 SVD operation
The SVD circuit compares the criteria voltage set by
software and the supply voltage (VDD–VSS) and sets
its results into the SVDDT latch. By reading the
data of this SVDDT latch, it can be determined by
means of software whether the supply voltage is
normal or has dropped.
The criteria voltage can be set for the 16 types
shown in Table 5.14.2.1 by the SVDS3–SVDS0
registers.
Table 5.14.2.1 Criteria voltage setting
SVDS3
1
0
Criteria
voltage (V)
4.35
4.17
4.00
3.83
3.67
3.50
3.33
3.17
3.00
2.83
2.67
2.50
2.33
2.17
2.00
1.83
SVDS2
1
0
1
0
SVDS1
1
0
1
0
1
0
1
0
SVDS0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
When the SVDON register is set to "1", source
voltage detection by the SVD circuit is executed. As
soon as the SVDON register is reset to "0", the result
is loaded to the SVDDT latch and the SVD circuit
goes OFF.
To obtain a stable detection result, the SVD circuit
must be ON for at least 100 sec. So, to obtain the
SVD detection result, follow the programming
sequence below.
1. Set SVDON to "1"
2. Maintain for 100 sec minimum
3. Set SVDON to "0"
4. Read SVDDT
When the SVD circuit is ON, the IC draws a large
current, so keep the SVD circuit off unless it is.
Fig. 5.14.1.1 Configuration of SVD circuit
V
SVD circuit
Detection output
Data
bus
DD
VSS
SVDDT
SVDON
SVDS3
|
SVDS0
Criteria voltage
setting circuit
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