參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 123/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
44
EPSON
S1C88848 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
5.7 Serial Interface
5.7.1 Configuration of serial interface
The S1C88848 incorporates a full duplex serial
interface (when asynchronous system is selected)
that allows the user to select either clock synchro-
nous system or asynchronous system.
The data transfer method can be selected in soft-
ware.
When the clock synchronous system is selected, 8-
bit data transfer is possible.
When the asynchronous system is selected, either 7-
bit or 8-bit data transfer is possible, and a parity
check of received data and the addition of a parity
bit for transmitting data can automatically be done
by selecting in software.
Figure 5.7.1.1 shows the configuration of the serial
interface.
Serial interface input/output terminals, SIN, SOUT,
_________
SCLK and SRDY are shared with I/O ports P10–P13.
In order to utilize these terminals for the serial
interface input/output terminals, proper settings
have to be made with registers ESIF, SMD0 and
SMD1. (At initial reset, these terminals are set as I/O
port terminals.)
The direction of I/O port terminals set for serial
interface input/output terminals are determined by
the signal and transfer mode for each terminal.
Furthermore, the settings for the corresponding I/O
control registers for the I/O ports become invalid.
SIN and SOUT are serial data input and output
terminals which function identically in clock
synchronous system and asynchronous system.
_________
SCLK is exclusively for use with clock synchronous
system and functions as a synchronous clock input/
_________
output terminal. SRDY is exclusively for use in clock
synchronous slave mode and functions as a send-
receive ready signal output terminal.
_________
When asynchronous system is selected, since SCLK
_________
and SRDY are superfluous, the I/O port terminals
P12 and P13 can be used as I/O ports.
In the same way, when clock synchronous master
_________
mode is selected, since SRDY is superfluous, the I/O
port terminal P13 can be used as I/O port.
Table 5.7.1.1 Configuration of input/output terminals
Fig. 5.7.1.1 Configuration of serial interface
Terminal
When serial interface is selected
P10
P11
P12
P13
SIN
SOUT
SCLK
SRDY
* The terminals used may vary depending on the transfer mode.
fOSC3
Data bus
SOUT(P11)
Serial I/O control
& status register
Received
data buffer
Interrupt
control circuit
Serial input
control circuit
Received data
shift register
Transmitting data
shift register
Serial output
control circuit
SIN(P10)
Clock
control circuit
READY output
control circuit
SCLK(P12)
Error detection
circuit
SRDY(P13)
Start bit
detection circuit
Programmable timer 1 underflow signal
Interrupt
request
OSC3 oscillation circuit
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