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參數(shù)資料
| 型號： | S1C88848D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192 |
| 封裝： | DIE-192 |
| 文件頁數(shù)： | 126/174頁 |
| 文件大?。?/td> | 1304K |
| 代理商： | S1C88848D0A0100 |
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S1C88848 TECHNICAL MANUAL
EPSON
47
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
5.7.5 Transmit-receive control
Below is a description of the registers which handle
transmit-receive control. With respect to transmit-
receive control procedures and operations, please
refer to the following sections in which these are
discussed on a mode by mode basis.
■ Shift register and received data buffer
Exclusive shift registers for transmitting and
receiving are installed in this serial interface.
Consequently, duplex communication simultane-
ous transmit and receive is possible when the
asynchronous system is selected.
Data being transmitted are written to TRXD0–
TRXD7 and converted to serial through the shift
register and is output from the SOUT terminal.
In the reception section, a received data buffer is
installed separate from the shift register.
Data being received are input to the SIN terminal
and is converted to parallel through the shift
register and written to the received data buffer.
Since the received data buffer can be read even
during serial input operation, the continuous data
is received efficiently.
However, since buffer functions are not used in
clock synchronous mode, be sure to read out data
before the next data reception begins.
■ Transmit enable register and transmit
control bit
For transmitting control, use the transmit enable
register TXEN and transmit control bit TXTRG.
The transmit enable register TXEN is used to set the
transmitting enable/disable status. When "1" is
written to this register to set the transmitting enable
status, clock input to the shift register is enabled
and the system is ready to transmit data. In the
clock synchronous mode, synchronous clock input/
_________
output from the SCLK terminal is also enabled.
The transmit control bit TXTRG is used as the
trigger to start transmitting data.
Data to be transmitted is written to the transmit
data shift register, and when transmitting prepara-
tions a recomplete, "1" is written to TXTRG where-
upon data transmitting begins.
When interrupt has been enabled, an interrupt is
generated when the transmission is completed. If
there is subsequent data to be transmitted it can be
sent using this interrupt.
In addition, TXTRG can be read as the status. When
set to "1", it indicates transmitting operation, and
"0" indicates transmitting stop.
For details on timing, see the timing chart which
gives the timing for each mode.
When not transmitting, set TXEN to "0" to disable
transmitting status.
■ Receive enable register, receive control bit
For receiving control, use the receive enable register
RXEN and receive control bit RXTRG.
Receive enable register RXEN is used to set receiv-
ing enable/disable status. When "1" is written into
this register to set the receiving enable status, clock
input to the shift register is enabled and the system
is ready to receive data. In the clock synchronous
mode, synchronous clock input/output from the
_________
SCLK terminal is also enabled.
With the above setting, receiving begins and serial
data input from the SIN terminal goes to the shift
register.
The operation of the receive control bit RXTRG is
slightly different depending on whether a clock
synchronous system or an asynchronous system is
being used.
In the clock synchronous system, the receive
control bit RXTRG is used as the trigger to start
receiving data.
When received data has been read and the prepara-
tion for next data receiving is completed, write "1"
into RXTRG to start receiving. (When "1" is written
_________
to RXTRG in slave mode, SRDY switches to "0".)
In an asynchronous system, RXTRG is used to
prepare for next data receiving. After reading the
received data from the received data buffer, write
"1" into RXTRG to signify that the received data
buffer is empty. If "1" is not written into RXTRG,
the overrun error flag OER will be set to "1" when
the next receiving operation is completed. (An
overrun error will be generated when receiving is
completed between reading the received data and
the writing of "1" to RXTRG.)
In addition, RXTRG can be read as the status. In
either clock synchronous mode or asynchronous
mode, when RXTRG is set to "1", it indicates
receiving operation and when set to "0", it indicates
that receiving has stopped.
For details on timing, see the timing chart which
gives the timing for each mode.
When you do not receive, set RXEN to "0" to disable
receiving status.
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