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參數(shù)資料
| 型號(hào)： | NAND08GW3B2CZL1F |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52 |
| 封裝： | 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52 |
| 文件頁數(shù)： | 8/72頁 |
| 文件大?。?/td> | 1919K |
| 代理商： | NAND08GW3B2CZL1F |
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Signal descriptions
NAND04G-B2D, NAND08G-BxC
3
Signal descriptions
See Figure 2: Logic diagram and Table 3: Signal names for a brief overview of the signals
connected to this device. The NAND08G-B4C devices have two separate sets of signals for
each 4-Gbit die.
3.1
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 input the selected address, output the data during a read operation, or
input a command or data during a write operation. The inputs are latched on the rising edge
of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are
disabled.
3.2
Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They output the data during a read
operation or input data during a write operation. Command and address inputs only require
I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3
Address latch enable (AL)
The address latch enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
3.4
Command latch enable (CL)
The command latch enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
3.5
Chip enable (E)
The Chip Enable input, E, activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, VIL, the device is selected. If Chip Enable goes
High, VIH, while the device is busy, the device remains selected and does not go into
standby mode.
3.6
Read enable (R)
The Read Enable pin, R, controls the sequential data output during read operations. Data is
valid tRLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NAND08GW3B4BN6E | 制造商:Micron Technology Inc 功能描述:NAND - Trays |
| NAND08GW3B4BN6F | 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel |
| NAND08GW3B4CN1F | 制造商:Micron Technology Inc 功能描述:NAND - Trays |
| NAND08GW3B4CZL6E | 制造商:Micron Technology Inc 功能描述:NAND - Trays |
| NAND08GW3C2AE01 | 功能描述:閃存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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