參數(shù)資料
型號(hào): NAND08GW3B2CZL1F
廠商: NUMONYX
元件分類: PROM
英文描述: 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52
封裝: 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52
文件頁數(shù): 27/72頁
文件大?。?/td> 1919K
代理商: NAND08GW3B2CZL1F
NAND04G-B2D, NAND08G-BxC
Device operations
An erase operation consists of the following three steps (refer to Figure 18: Block erase):
1.
One bus cycle is required to set up the Block Erase command. Only addresses A18-
A28 are used; all other address inputs are ignored
2.
Three bus cycles are then required to load the address of the block to be erased. Refer
to Table 8: Address definition (x8 devices) for the block addresses of each device
3.
One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
The operation is initiated on the rising edge of Write Enable, W, after the Confirm command
is issued. The P/E/R controller handles block erase and implements the verify process.
During the block erase operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the write status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Figure 18.
Block erase
I/O
RB
Block Address
Inputs
SR0
ai07593
D0h
70h
60h
Block Erase
Setup Code
Confirm
Code
Read Status Register
Busy
tBLBH3
(Erase Busy time)
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