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參數(shù)資料
| 型號： | NAND08GW3B2CZL1F |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52 |
| 封裝： | 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52 |
| 文件頁數(shù)： | 32/72頁 |
| 文件大?。?/td> | 1919K |
| 代理商： | NAND08GW3B2CZL1F |
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Device operations
NAND04G-B2D, NAND08G-BxC
6.12
Read status enhanced
In NAND flash devices with multiplane architecture, it is possible to independently read the
status register of a single plane using the Read Status Enhanced command. If the error bit
of the status register, SR0, reports an error during or after a multiplane operation, the Read
Status Enhanced command is used to know which of the two planes contains the page that
failed the operation. Three address cycles are required to address the selected block and
page (A12-A28 for x8 devices and A11-A27 for x16 devices).
The output of the Read Status Enhanced command has the same coding as the Read
enhanced waveform.
6.13
Read EDC status register
The devices contain an EDC status register, which provides information on the errors that
occurred during the read cycles of the copy back and multiplane copy back operations. In
the case of multiplane copy back program, it is not possible to distinguish which of the two
read operations caused the error.
The EDCS status register is read by issuing the Read EDC Status Register command.
After issuing the Read EDC Status Register command, a read cycle outputs the content of
the EDC status register to the I/O pins on the falling edge of Chip Enable or Read Enable
signals, whichever occurs last. The operation is similar to Read Status Register command.
Table 15: EDC status register bits summarizes the EDC status register bits. See Figure 30
for a description of Read EDC Status Register waveforms.
Table 15.
EDC status register bits
Bit
Name
Logic level
Definition
0
Pass/fail
‘1’
Copy back or multiplane copy back
operation failed
‘0’
Copy back or multiplane copy back
operation succeeded
1
EDC status
‘1’
Error
‘0’
No error
2
EDC validity
‘1’
Valid
‘0’
Invalid
3
Reserved
‘don’t care’
–
4
Reserved
‘don’t care’
–
5
Ready/busy(1)
1.
See Table 14: Status register bits for a description of SR5 and SR6 bits.
‘1’
Ready
‘0’
Busy
6
Ready/busy(1)
‘1’
Ready
‘0’
Busy
7
Write protect
‘1’
Not protected
‘0’
Protected
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參數(shù)描述 |
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