參數(shù)資料
型號(hào)： NAND08GW3B2CZL1F
廠商： NUMONYX
元件分類： PROM
英文描述： 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52
封裝： 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52
文件頁(yè)數(shù)： 10/72頁(yè)
文件大小： 1919K
代理商： NAND08GW3B2CZL1F
Bus operations
NAND04G-B2D, NAND08G-BxC
4
Bus operations
There are six standard bus operations that control the memory, as described in this section.
SeeTable 5: Bus operations for a summary of these operations.
Typically, glitches of less than 5 ns on Chip Enable, Write Enable, and Read Enable are
ignored by the memory and do not affect bus operations.
4.1
Command input
Command input bus operations give commands to the memory.
Commands are accepted when Chip Enable is Low, Command Latch Enable is High,
Address Latch Enable is Low, and Read Enable is High. They are latched on the rising edge
of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 25 and Table 30 for details of the timings requirements.
4.2
Address input
Address input bus operations input the memory addresses. Five bus cycles are required to
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low, and Read Enable is High. They are latched on the rising
edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input addresses.
See Figure 26 and Table 30 for details of the timings requirements.
4.3
Data input
Data input bus operations input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low, and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 27 and Table 30 and Table 31 for details of the timings requirements.
4.4
Data output
Data output bus operations read the data in the memory array, the status register, the
electronic signature, and the unique identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
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NAND08GW3C2AE01 功能描述:閃存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問(wèn)時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
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