參數(shù)資料
型號(hào): NAND08GW3B2CZL1F
廠商: NUMONYX
元件分類(lèi): PROM
英文描述: 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52
封裝: 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52
文件頁(yè)數(shù): 40/72頁(yè)
文件大?。?/td> 1919K
代理商: NAND08GW3B2CZL1F
NAND04G-B2D, NAND08G-BxC
Concurrent operations and extended read status
7
Concurrent operations and extended read status
The NAND08G-BxC devices are composed of two 4-Gbit dice stacked together. This
configuration allows the devices to support concurrent operations, which means that while
performing an operation in one die (erase, read, program, etc.), another operation is
possible in the other die.
The standard read status register operation returns the status of the NAND08G-BxC device.
To provide information on each 4-Gbit die, the NAND08G-BxC devices feature an Extended
Read Status Register command that independently checks the status of each NAND04G-
B2D.
The following steps are required to perform concurrent operations:
1.
Select one of the two dice by setting the most significant address bit A30 to ‘0’ or ‘1’
2.
Execute one operation on this die
3.
Launch a concurrent operation on the other die
4.
Check the status of these operations by performing an extended read status register
operation.
All combinations of operations are possible except read while read. This is due to the fact
that the input/output bus is common to both dice.
Refer to Table 22 for the description of the Extended Read Status Register command
sequence, and to Table 14. for the definition of the status register bits.
8
Data protection
The devices feature a Write Protect, WP, pin, which can be used to protect the device
against program and erase operations. It is recommended to keep WP at VIL during power-
up and power-down.
Table 22.
Extended Read Status Register commands
Command
Address range
1 bus write cycle
Read 1st die status
Address
≤ 0x3FFFFFFF
F2h
Read 2nd die status
0x3FFFFFFF < Address
≤ 0x7FFFFFF
F3h
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