參數(shù)資料
型號(hào): NAND08GW3B2CZL1F
廠商: NUMONYX
元件分類(lèi): PROM
英文描述: 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52
封裝: 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52
文件頁(yè)數(shù): 18/72頁(yè)
文件大?。?/td> 1919K
代理商: NAND08GW3B2CZL1F
NAND04G-B2D, NAND08G-BxC
Device operations
After the Sequential Cache Read or Random Cache Read command has been issued, the
Ready/Busy signal goes Low and the status register bits are set to SR5 =' 0' and SR6 ='0'
for a period of cache read busy time, tRCBSY, while the device copies the next page into the
cache register.
After the cache read busy time has passed, the Ready/Busy signal goes High and the status
register bits are set to SR5 = '0' and SR6 = '1', signifying that the cache register is ready to
download new data. Data of the previously read page can be output from the page buffer by
toggling the Read Enable signal. Data output always begins at column address 00h, but the
Random Data Output command is also supported.
Figure 9.
Cache read (sequential) operation
Figure 10.
Cache read (random) operation
I/O0-7
RB
Address
Inputs
ai13176b
00h
30h
tBLBH1
(Read Busy time)
R
tRCBSY
31h
3Fh
Data
Outputs
Data
Outputs
(Read Cache Busy time)
Read
Setup
Code
Read
Code
Repeat as many times as ncessary.
Cache
Read
Sequential
Code
Exit
Cache
Read
Code
Busy
I/O0-7
RB
Address
Inputs
ai13176c
00h
30h
tBLBH1
(Read Busy time)
R
tRCBSY
00h
Data
Outputs
(Read Cache Busy time)
Read
Setup
Code
Read
Code
Repeat as many times as ncessary.
Read
Setup
Code
Exit
Cache
Read
Code
Busy
31h
Enhanced
Cache
Read
(random)
Code
3Fh
Data
Outputs
Address
Inputs
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