參數(shù)資料
型號(hào)： NAND08GW3B2CZL1F
廠商： NUMONYX
元件分類： PROM
英文描述： 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52
封裝： 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52
文件頁數(shù)： 30/72頁
文件大小： 1919K
代理商： NAND08GW3B2CZL1F
Device operations
NAND04G-B2D, NAND08G-BxC
Table 13.
Address definition for EDC units (x16 devices)
6.10
Reset
The Reset command is used to reset the command interface and status register. If the
Reset command is issued during any operation, the operation is aborted. If the aborted
operation is a program or erase, the contents of the memory locations being modified are no
longer valid as the data is partially programmed or erased.
If the device has already been reset, then the new Reset command is not accepted.
The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value
of tBLBH4 depends on the operation that the device was performing when the command was
issued. Refer to Table 31 for the values.
6.11
Read status register
The devices contain a status register that provides information on the current or previous
program or erase operation. The various bits in the status register convey information and
errors on the operation.
The status register is read by issuing the Read Status Register command. The status
register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the status register.
After the Read Status Register command has been issued, the device remains in read
status register mode until another command is issued. Therefore, if a Read Status Register
command is issued during a random read cycle, a new Read command must be issued to
continue with a page read operation.
The status register bits are summarized in Table 14: Status register bits. Refer to Table 14 in
conjunction with the following sections.
6.11.1
Write protection bit (SR7)
The write protection bit identifies if the device is protected or not. If the write protection bit is
set to ‘1’, the device is not protected and program or erase operations are allowed. If the
write protection bit is set to ‘0’ the device is protected and program or erase operations are
not allowed.
EDC unit
Main area
Spare area
Area name
Column address
Area name
Column address
1st 264-word EDC unit
A
0 to 255
E
1024 to 1031
2nd 264-word EDC unit
B
256 to 511
F
1032 to 1039
3rd 264-word EDC unit
C
512 to 767
G
1040 to 1047
4th 264-word EDC unit
D
768 to 1023
H
1048 to 1055
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NAND08GW3B4BN6E 制造商:Micron Technology Inc 功能描述:NAND - Trays
NAND08GW3B4BN6F 制造商:Micron Technology Inc 功能描述:NAND - Tape and Reel
NAND08GW3B4CN1F 制造商:Micron Technology Inc 功能描述:NAND - Trays
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NAND08GW3C2AE01 功能描述:閃存 NAND & S.MEDIA FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
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