參數(shù)資料
型號: NAND08GW3B2CZL1F
廠商: NUMONYX
元件分類: PROM
英文描述: 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52
封裝: 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52
文件頁數(shù): 11/72頁
文件大小: 1919K
代理商: NAND08GW3B2CZL1F
NAND04G-B2D, NAND08G-BxC
Bus operations
If the Read Enable pulse frequency is lower then 33 MHz (tRLRL higher than 30 ns), the
output data is latched on the rising edge of Read Enable signal (see Figure 28).
For higher frequencies (tRLRL lower than 30 ns), the EDO (extended data out) mode must be
used. In this mode, data output bus operations are valid on the input/output bus for a time of
tRLQX after the falling edge of Read Enable signal (see Figure 29).
See Table 31 for details on the timings requirements.
4.5
Write protect
Write protect bus operations protect the memory against program or erase operations.
When the Write Protect signal is Low the device does not accept program or erase
operations, and, therefore, the contents of the memory array cannot be altered. The Write
Protect signal is not latched by Write Enable to ensure protection, even during power-up.
4.6
Standby
When Chip Enable is High the memory enters standby mode, the device is deselected,
outputs are disabled, and power consumption is reduced.
Table 5.
Bus operations
Bus operation
E
AL
CL
R
W
WP
I/O0 - I/O7
I/O8 - I/O15(1)
1.
Only for x16 devices.
Command input
VIL
VIH
Rising
X(2)
2.
WP must be VIH when issuing a Program or Erase command.
Command
X
Address input
VIL
VIH
VIL
VIH
Rising
X
Address
X
Data input
VIL
VIH
Rising
VIH
Data input
Data output
VIL
Falling
VIH
X
Data output
Write protect
X
VIL
XX
Standby
VIH
XX
X
VIL/VDD
XX
Table 6.
Address insertion (x8 devices)
Bus
cycle(1)
1.
Any additional address input cycles are ignored.
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
A7
A6
A5
A4
A3
A2
A1
A0
2nd
VIL
A11
A10
A9
A8
3rd
A19
A18
A17
A16
A15
A14
A13
A12
4th
A27
A26
A25
A24
A23
A22
A21
A20
5th
VIL
A30(2)
2.
A30 is only valid for the NAND08G-BxC devices.
A29
A28
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