參數(shù)資料
型號: NAND08GW3B2CZL1F
廠商: NUMONYX
元件分類: PROM
英文描述: 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52
封裝: 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52
文件頁數(shù): 6/72頁
文件大?。?/td> 1919K
代理商: NAND08GW3B2CZL1F
Memory array organization
NAND04G-B2D, NAND08G-BxC
2
Memory array organization
The memory array of the devices is made up of NAND structures where 32 cells are
connected in series. It is organized into blocks where each block contains 64 pages. The
array is split into two areas, the main area, and the spare area. The main area of the array is
used to store data, and the spare area typically stores error correction codes, software flags,
or bad block identification.
In x8 devices, the pages are split into a 2048-byte main area and a spare area of 64 bytes.
In x16 devices, the pages are split into a 1024-word main area and a spare area of
Bad blocks
In x8 devices, the NAND flash 2112-byte/1056-word page devices may contain bad blocks,
which are blocks that contain one or more invalid bits whose reliability is not guaranteed.
Additional bad blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 9.1: Bad block
management for more details).
Table 4 shows the minimum number of valid blocks. The values shown include both the bad
blocks that are present when the device is shipped and the bad blocks that could develop
later on.
These blocks need to be managed using bad blocks management, block replacement, or
error correction codes (refer to Section 9: Software algorithms).
Table 4.
Valid blocks
Density of device
Min
Max
4 Gbits
4016
4096
8Gbits(1)
1.
The NAND08G-BxC devices are composed of two 4-Gbit dice. The minimum number of valid blocks is
4016 for each die.
8032
8192
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