參數(shù)資料
型號: NAND08GW3B2CZL1F
廠商: NUMONYX
元件分類: PROM
英文描述: 1G X 8 FLASH 3V PROM, 25000 ns, PBGA52
封裝: 12 X 17 MM, 1 MM PITCH, LEAD FREE, LGA-52
文件頁數(shù): 28/72頁
文件大?。?/td> 1919K
代理商: NAND08GW3B2CZL1F
Device operations
NAND04G-B2D, NAND08G-BxC
6.8
Multiplane block erase
The multiplane block erase operation allows the erasure of two blocks in parallel, one in
each plane.
This operation consists of the following three steps (refer to Figure 19: Multiplane block
1.
10 bus cycles are required to set up the Block Erase command and load the addresses
of the blocks to be erased. The setup command followed by the address of the block to
be erased must be issued for each block. tIEBSY busy time is required between the
insertion of first and the second block addresses. As for multiplane page program
operations, the address of the first and second page must be within the first plane
(A18 = 0 for x8 devices, A17 = 0 for x16 devices) and second plane (A18 = 1 for x8
devices, A17 = 1 for x16 devices), respectively.
2.
1 bus cycle is then required to issue the Multiplane Block Erase Confirm command and
start the P/E/R controller.
If the multiplane block erase fails, an error is signaled on bit SR0 of the status register. To
know which page of the two planes failed, the Read Status Enhanced command must be
issued twice, once for each plane (see Section 6.12).
Figure 19.
Multiplane block erase
1.
This address scheme refers to x8 devices. Please remember to use the appropriate scheme for x16 devices.
I/O
RB
Block address
inputs
SR0
ai13173c
D0h
70h
60h
Block Erase
Setup code
Confirm
code
Read Status
register
Busy
tBLBH3
(Erase Busy time)
A18=0
Block address
inputs
Block Erase
Setup code
A18=1
A12-A17=0
A17-A29=0
60h
A12-A17=0
A17-A29=valid
a) Traditional sequence
W
CL
AL
R
60h R1A R2A R3A D1h
60h R1B R2B R3B
I/O 0-7
RB
Busy
tIPBSY
Busy
tBLBH2
(Program Busy time)
b) ONFI 1.0 sequence.
D0h
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