參數(shù)資料
型號： HYB18T512800AC-5
廠商： INFINEON TECHNOLOGIES AG
英文描述： M39012 MIL RF CONNECTOR
中文描述： 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁數(shù)： 85/96頁
文件大?。?/td> 2153K
代理商： HYB18T512800AC-5
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Reference Loads, Setup & Hold Timing Definition and Slew Rate Derating
Data Sheet
85
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
Figure 69
Data, Setup and Hold Time Diagram
8.3.3
Setup (
t
DS
) nominal slew rate for a rising signal is
defined as the slew rate between the last crossing of
V
REF(dc)
and the first crossing of
V
IH(ac)min
. Setup (
t
DS
)
nominal slew rate for a falling signal is defined as the
slew rate between the last crossing of
V
REF(dc)
and the
first crossing of
V
IL(ac)max
. If the actual signal is always
earlier than the nominal slew rate line between shaded
‘
V
REF(dc)
to ac region’, use nominal slew rate for derating
value.(
Figure 70
)
If the actual signal is later than the nominal slew rate
line anywhere between shaded ‘
V
REF(dc)
to ac region’,
the slew rate of a tangent line to the actual signal from
the ac level to dc level is used for derating value.
(
Figure 71
)
Slew Rate Definition for Input and Data Setup and Hold Times
Hold (
t
DH
) nominal slew rate for a rising signal is defined
as the slew rate between the last crossing of
V
IL(dc)max
and the first crossing of
V
REF(dc)
. Hold (
t
DH
) nominal slew
rate for a falling signal is defined as the slew rate
between the last crossing of
V
IH(dc)min
and the first
crossing of
V
REF(dc)
. If the actual signal is always later
than the nominal slew rate line between shaded ‘dc
level to
V
REF(dc)
region’, use nominal slew rate for
derating value. (
Figure 72
)
If the actual signal is earlier than the nominal slew rate
line anywhere between shaded ‘dc to
V
REF(dc)
region’,
the slew rate of a tangent line to the actual signal from
the dc level to
V
REF(dc)
level is used for derating
value.(
Figure 73
)
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF
V
IL(dc)
max
V
IL(ac)
max
V
SS
tDStDH
tDS
V
REF
tDH
DQS
DQS
DQS
Differential Input
Waveform
Single-ended Input
Waveform
相關(guān)PDF資料
PDF描述
HYB18T512800AC DDR2 Registered Memory Modules
HYB18T512800AF DDR2 Registered Memory Modules
HYB18T512800AF-37 512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512800AF-5 512-Mbit Double-Data-Rate-Two SDRAM
HYB25D128160CE-5 128 Mbit Double Data Rate SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T512800AF-3S 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84
HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
HYB18T512800BF-3.7 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF)
HYB18T512800BF-3S 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR)
HYB25D128160AT-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
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