參數(shù)資料
型號: HYB18T512800AC-5
廠商: INFINEON TECHNOLOGIES AG
英文描述: M39012 MIL RF CONNECTOR
中文描述: 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁數(shù): 26/96頁
文件大小: 2153K
代理商: HYB18T512800AC-5
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Data Sheet
26
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
A0 is used for DLL enable or disable. A1 is used for
enabling half-strength data-output driver. A2 and A6
enables ODT (On-Die termination) and sets the Rtt
value. A[5:3] are used for additive latency settings and
A[9:7] enables the OCD impedance adjustment mode.
A10 enables or disables the differential DQS and
RDQS signals, A11 disables or enables RDQS.
Address bit A12 have to be set to “l(fā)ow” for normal
operation. With A12 set to “high” the SDRAM outputs
are disabled and in Hi-Z. “High” on BA0 and “l(fā)ow” for
BA1 have to be set to access the EMRS(1). A13 and all
“higher” address bits have to be set to “l(fā)ow” for
compatibility with other DDR2 memory products with
higher memory densities. Refer to
Mode Register
Definition (BA[1:0] = 00
B
)
.
Single-ended and Differential Data Strobe Signals
Table 8
lists all possible combinations for DQS, DQS,
RDQS, RQDS which can be programmed by A[11:10]
address bits in EMRS. RDQS and RDQS are available
in
×
8 components only.
If RDQS is enabled in
×
8 components, the DM function
is disabled. RDQS is active for reads and don’t care for
writes.
DLL Enable/Disable
OCD
Program
[9:7]
w
Off-Chip Driver Calibration Program
Every calibration mode command should be followed by “OCD calibration mode exit”
before any other command will be issued; see
Chapter 2.3
.
000
OCD calibration mode exit, maintain setting
001
Drive 1
010
Drive 0
100
Adjust mode
Note: When Adjust Mode is issued, AL from previously set value must be applied.
111
OCD calibration default
Note: After setting to default, OCD mode needs to be exited by setting A[9:7] to 000.
Complement Query Strobe (DQS, RDQS Output)
If enabled the complement query strobe (DQS output) is driven high one clock cycle
before valid query data (DQ) is driven onto the data bus; see
Chapter 2.6.3
.
0
Enable
1
Disable
Read Data Strobe Output (RDQS, RDQS)
0
Disable
1
Enable
Output Disable
Disabling the DRAM outputs (
DQ, DQS, DQS, RDQS, RDQS
) allows users to
measure
I
DD
during Read operations without including the output buffer current.
0
Output buffers enabled
1
Output buffers disabled
DQS
10
w
RDQS
11
w
Qoff
12
w
1) w = write only register bits
Field
Bits
Type
1)
Description
(cont’d)
Table 8
EMRS(1)
A11
(RDQS Enable)
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
Single-ended and Differential Data Strobe Signals
Strobe Function Matrix
A10
(DQS Enable)
0 (Enable)
DM
1 (Disable)
DM
0 (Enable)
RDQS
1 (Disable)
RDQS
Signaling
RDQS/DM
RDQS
DQS
DQS
Hi-Z
Hi-Z
RDQS
Hi-Z
DQS
DQS
DQS
DQS
DQS
Hi-Z
DQS
Hi-Z
differential DQS signals
single-ended DQS signals
differential DQS signals
single-ended DQS signals
相關PDF資料
PDF描述
HYB18T512800AC DDR2 Registered Memory Modules
HYB18T512800AF DDR2 Registered Memory Modules
HYB18T512800AF-37 512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512800AF-5 512-Mbit Double-Data-Rate-Two SDRAM
HYB25D128160CE-5 128 Mbit Double Data Rate SDRAM
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