參數(shù)資料
型號(hào)： HYB18T512800AC-5
廠商： INFINEON TECHNOLOGIES AG
英文描述： M39012 MIL RF CONNECTOR
中文描述： 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁數(shù)： 38/96頁
文件大小： 2153K
代理商： HYB18T512800AC-5
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Data Sheet
38
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
Figure 20
Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read
delay <
t
RCDmin
: AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL -1) = 4, BL = 8
Figure 21
Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read
delay =
t
RCDmin
: AL = 0, CL = 3, RL = (AL + CL) = 3, WL = (RL -1) = 2, BL = 4
Figure 22
Read to Write Timing Example : Read followed by a write to the same bank, Activate to Read
delay >
t
RCDmin
: AL = 1, CL = 3, RL = 4, WL = 3, BL = 4
2.6.2
Burst mode operation is used to provide a constant flow
of data to memory locations (write cycle), or from
memory locations (read cycle). The parameters that
define how the burst mode will operate are burst
sequence and burst length. The DDR2 SDRAM
supports 4 bit and 8 bit burst modes only. For 8 bit burst
Burst Mode Operation
mode, full interleave address ordering is supported,
however, sequential address ordering is nibble based
for ease of implementation. The burst length is
programmable and defined by the addresses A[2:0] of
the MRS. The burst type, either sequential or
interleaved, is programmable and defined by the
Bank A
tRCD
CL = 3
AL = 2
RL = AL + CL = 5
WL = RL -1 = 4
PostCAS3
CMD
DQ
DQS,
DQS
CK, CK
0
2
3
4
5
1
6
7
8
9
10
11
Read
Write
Din0
Din1
Din2
Din3
Dout0
Dout1
Dout2
Dout3
Dout4
Dout5
Dout6
Dout7
12
Activate
Read
Write
tRCD
CL = 3
AL = 0
RL = AL + CL = 3
WL = RL -1 = 2
PostCAS2
CMD
DQ
DQS,
DQS
CK, CK
0
2
3
4
5
1
6
7
8
9
10
11
Dout0
Dout1
Dout2
Dout3
Din0
Din1
Din2
Din3
Bank A
tRCD > tRCDmin.
RL = 4
WL = 3
PostCAS5
CMD
DQ
DQS,
DQS
CK, CK
0
2
3
4
5
1
6
7
8
9
10
11
Read
Dout0
Dout1
Dout2
Dout3
Din0
Din1
Din2
Din3
Write
Bank A
12
13
相關(guān)PDF資料
PDF描述
HYB18T512800AC DDR2 Registered Memory Modules
HYB18T512800AF DDR2 Registered Memory Modules
HYB18T512800AF-37 512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512800AF-5 512-Mbit Double-Data-Rate-Two SDRAM
HYB25D128160CE-5 128 Mbit Double Data Rate SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T512800AF-3S 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84
HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
HYB18T512800BF-3.7 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF)
HYB18T512800BF-3S 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR)
HYB25D128160AT-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
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