參數(shù)資料
型號： HYB18T512800AC-5
廠商： INFINEON TECHNOLOGIES AG
英文描述： M39012 MIL RF CONNECTOR
中文描述： 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁數(shù)： 36/96頁
文件大?。?/td> 2153K
代理商： HYB18T512800AC-5
Col. Addr.
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Data Sheet
36
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
respectively. The minimum time interval between
successive Bank Activate commands to the same bank
is determined (
t
RC
). The minimum time interval between
Bank Active commands, to any other bank, is the Bank
A to Bank B delay time (
t
RRD
).
In order to ensure that components with 8 internal
memory banks do not exceed the instantaneous
current supplying capability, certain restrictions on
operation of the 8 banks must be observed. There are
two rules.
One for restricting the number of sequential Active
commands that can be issued and another for allowing
more time for RAS precharge for a Precharge-All
command. The rules are as follows:
1. Sequential Bank Activation Restriction (JEDEC
ballot item 1293.15): No more than 4 banks may be
activated in a rolling
t
FAW
window. Converting to
clocks is done by deviding
t
FAW(ns)
by
t
CK(ns)
and
rounding up to next integer value. As an example of
the rolling window, if (
t
FAW
/
t
CK
) rounds up to 10
clocks, and an activate command is issued in clock
N, no more than three further activate commands
may be issued in clocks N + 1 through N + 9.
2. Precharge All Allowance:
t
RP
for a Precharge-All
command will equal to
t
RP
+ 1
t
CK
, where
t
RP
is the
value for a single bank precharge.
Figure 17
Bank Activate Command Cycle:
t
RCD
= 3, AL = 2,
t
RP
= 3,
t
RRD
= 2
2.6
Read and Write Commands and Access Modes
After a bank has been activated, a read or write cycle
can be executed. This is accomplished by setting RAS
high, CS and CAS low at the clock’s rising edge. WE
must also be defined at this time to determine whether
the access cycle is a read operation (WE high) or a
write operation (WE low). The DDR2 SDRAM provides
a wide variety of fast access modes. A single Read or
Write Command will initiate a serial read or write
operation on successive clock cycles at data rates of up
to 667 Mb/sec/pin for main memory. The boundary of
the burst cycle is restricted to specific segments of the
page length.
For example, the 32Mbit
×
4 I/O
×
4 Bank chip has a
page length of 2048 bits (defined by CA[9:0] & CA11).
In case of a 4-bit burst operation (burst length = 4) the
page length of 2048 is divided into 512 uniquely
addressable segments (4-bits
×
4 I/O each). The 4-bit
burst operation will occur entirely within one of the 512
segments (defined by CA[8:0] beginning with the
column address supplied to the device during the Read
or Write Command (CA[9:0] & A11). The second, third
and fourth access will also occur within this segment,
however, the burst order is a function of the starting
address, and the burst sequence.
In case of a 8-bit burst operation (burst length = 8) the
page length of 2048 is divided into 256 uniquely
addressable double segments (8-bits
×
4 I/O each).
The 8-bit burst operation will occur entirely within one
of the 256 double segments (defined by CA[7:0])
Address
NOP
Command
T
0
T
2
T
1
T
3
T
4
Col. Addr.
Bank A
Row Addr.
Bank B
Bank B
Internal RAS-CAS delay tRCDmin.
Bank A to Bank B delay tRRD.
Activate
Bank B
Read A
Posted CAS
Activate
Bank A
Read B
Posted CAS
Read A Begins
Row Addr.
Bank A
Addr.
Bank A
Precharge
Bank A
NOP
Addr.
Bank B
Precharge
Bank B
Row Addr.
Bank A
Activate
Bank A
tRP Row Precharge Time (Bank A)
tRC Row Cycle Time (Bank A)
T
n
Tn+1
Tn+2
Tn+3
ACT
tRAS Row Active Time (Bank A)
additive latency AL=2
CK, CK
tCCD
相關(guān)PDF資料
PDF描述
HYB18T512800AC DDR2 Registered Memory Modules
HYB18T512800AF DDR2 Registered Memory Modules
HYB18T512800AF-37 512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512800AF-5 512-Mbit Double-Data-Rate-Two SDRAM
HYB25D128160CE-5 128 Mbit Double Data Rate SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T512800AF-3S 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84
HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
HYB18T512800BF-3.7 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF)
HYB18T512800BF-3S 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-MSOP 包裝:帶卷 (TR)
HYB25D128160AT-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*