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| 型號(hào)： | HYB18T512800AC-5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | M39012 MIL RF CONNECTOR |
| 中文描述： | 512兆雙數(shù)據(jù)速率2內(nèi)存 |
| 文件頁數(shù)： | 42/96頁 |
| 文件大?。?/td> | 2153K |
| 代理商： | HYB18T512800AC-5 |
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HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Data Sheet
42
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
Figure 27
Seamless Read Operation Example: RL = 5, AL = 2, CL = 3, BL = 4
The seamless read operation is supported by enabling a read command at every BL / 2 number of clocks. This
operation is allowed regardless of same or different banks as long as the banks are activated.
Figure 28
Seamless Read Operation Example: RL = 3, AL = 0, CL = 3, BL = 8 (non interrupting)
The seamless, non interrupting 8-bit read operation is supported by enabling a read command at every BL/2
number of clocks. This operation is allowed regardless of same or different banks as long as the banks are
activated.
2.6.4
The Write command is initiated by having CS, CAS and
WE low while holding RAS high at the rising edge of the
clock. The address inputs determine the starting
column address. Write latency (WL) is defined by a
read latency (RL) minus one and is equal to (AL + CL -
1). A data strobe signal (DQS) has to be driven low
(preamble) a time
t
WPRE
prior to the WL. The first data
bit of the burst cycle must be applied to the DQ pins at
the first rising edge of the DQS following the preamble.
The
t
DQSS
specification must be satisfied for write
cycles. The subsequent burst bit data are issued on
Write Command
successive edges of the DQS until the burst length is
completed. When the burst has finished, any additional
data supplied to the DQ pins will be ignored. The DQ
signal is ignored after the burst write operation is
complete. The time from the completion of the burst
write to bank precharge is named “write recovery time”
(
t
WR
) and is the time needed to store the write data into
the memory array.
t
WR
is an analog timing parameter
(see
AC & DC Operating Conditions
) and is not the
programmed value for WR in the MRS.
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ A
Post CAS
READ B
Post CAS
T
0
T
2
T
1
T
3
T
4
T
5
T
6
T
7
T
8
Dout A0
Dout A1
Dout A2
Dout A3
Dout B0
Dout B1
Dout B2
Dout B3
RL = 5
AL = 2
CL = 3
SBR523
CMD
DQ
DQS,
DQS
CK, CK
NOP
NOP
NOP
READ A
Post CAS
T
0
T
2
T
1
T
3
T
4
T
5
T
6
T
7
T
8
Dout A0
Dout A1
Dout A2
Dout A3
Dout A4
Dout A5
Dout A4
Dout A7
RL = 3
CL = 3
SBR_BL8
CMD
DQ
DQS,
DQS
READ B
Post CAS
Dout B0
Dout B1
Dout B2
Dout B3
Dout B4
Dout B5
Dout B6
Dout B7
NOP
NOP
NOP
NOP
NOP
NOP
NOP
T
9
T10
CK, CK
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