- 您現在的位置：買賣IC網 > PDF目錄370782 > HYB18T512800AC-5 (INFINEON TECHNOLOGIES AG) M39012 MIL RF CONNECTOR PDF資料下載
參數資料
| 型號： | HYB18T512800AC-5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | M39012 MIL RF CONNECTOR |
| 中文描述： | 512兆雙數據速率2內存 |
| 文件頁數： | 66/96頁 |
| 文件大小： | 2153K |
| 代理商： | HYB18T512800AC-5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁當前第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Truth Tables
Data Sheet
66
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
Table 17
Current State
1)
Clock Enable (CKE) Truth Table for Synchronous Transitions
CKE
Previous Cycle
6)
(N-1)
(N)
Power-Down
L
L
L
H
Self Refresh
L
L
L
H
Bank(s)
Active
All Banks Idle
H
L
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
4) CKE must be maintained high while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by
the refresh requirements
8) “X” means “don’t care (including floating around
V
REF
)” in Self Refresh and Power Down. However ODT must be driven
high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11) Minimum CKE high time is 3 clocks, minimum CKE low time is 3 clocks.
12)
V
REF
must be maintained during Self Refreh Operation
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR
period. Read commands may be issued only after
t
XSRD
(200 clocks) is satisfied.
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations,
Precharge or Refresh operations are in progress. See
Chapter 2.10
and
Chapter 2.9.2
for a detailed list of restrictions.
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
Command (N)
2)
3)
RAS, CAS, WE, CS
Action (N)
2)
Notes
4)5)
Current Cycle
6)
X
DESELECT or NOP Power-Down Exit
X
DESELECT or NOP Self Refresh Exit
DESELECT or NOP Active Power-Down Entry
Maintain Power-Down
7)8)11)
9)10)11)7)
Maintain Self Refresh
11)8)12)
9)13)14)12)
H
L
9)10)15)11)7)
DESELECT or NOP Precharge Power-Down
Entry
AUTOREFRESH
Self Refresh Entry
Refer to the Command Truth Table
9)10)15)11)
H
H
L
H
16)14)11)7)
Any State other
than
listed above
17)
Table 18
Name (Function)
Write Enable
Write Inhibit
Data Mask (DM) Truth Table
DM
L
H
DQs
Valid
X
Notes
1)
1)
Used to mask write data; provided coincident with the corresponding data.
1)
相關PDF資料 |
PDF描述 |
|---|---|
| HYB18T512800AC | DDR2 Registered Memory Modules |
| HYB18T512800AF | DDR2 Registered Memory Modules |
| HYB18T512800AF-37 | 512-Mbit Double-Data-Rate-Two SDRAM |
| HYB18T512800AF-5 | 512-Mbit Double-Data-Rate-Two SDRAM |
| HYB25D128160CE-5 | 128 Mbit Double Data Rate SDRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| HYB18T512800AF-3S | 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| HYB18T512800BF-2.5 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 產品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T512800BF-3.7 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應商設備封裝:8-DFN（2x3） 包裝:管件 產品目錄頁面:1445 (CN2011-ZH PDF) |
| HYB18T512800BF-3S | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-MSOP 包裝:帶卷 (TR) |
| HYB25D128160AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。