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參數(shù)資料
| 型號： | HYB18T512800AC-5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | M39012 MIL RF CONNECTOR |
| 中文描述： | 512兆雙數(shù)據(jù)速率2內(nèi)存 |
| 文件頁數(shù)： | 48/96頁 |
| 文件大小： | 2153K |
| 代理商： | HYB18T512800AC-5 |
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HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Data Sheet
48
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
2.7
Precharge Command
The Precharge Command is used to precharge or close
a bank that has been activated. The Precharge
Command is triggered when CS, RAS and WE are low
and CAS is high at the rising edge of the clock. The Pre-
charge Command can be used to precharge each bank
independently or all banks simultaneously. Three
address bits A10, BA0 and BA1 are used to define
which bank to precharge when the command is issued.
Note:The bank address assignment is the same for activating and precharging a specific bank.
2.7.1
The following rules apply as long as the
t
RTP
timing
parameter - Internal Read to Precharge Command
delay time - is less or equal two clocks, which is the
case for operating frequencies less or equal 266 Mhz
(DDR2 400 and 533 speed sorts):
Minimum Read to Precharge command spacing to the
same bank = AL + BL/2 clocks. For the earliest possible
precharge, the Precharge command may be issued on
the rising edge which is “Additive Latency (AL) + BL/2
clocks” after a Read Command, as long as the
minimum
t
RAS
timing is satisfied.
Read Operation Followed by a Precharge
A new bank active command may be issued to the
same bank if the following two conditions are satisfied
simultaneously:
1. The RAS precharge time (
t
RP
) has been satisfied
from the clock at which the precharge begins.
2. The RAS cycle time (
t
RC, min
) from the previous bank
activation has been satisfied.
For operating frequencies higher than 266 MHz,
t
RTP
becomes > 2 clocks and one additional clock cycle has
to be added for the minimum Read to Precharge
command spacing, which now becomes AL + BL/2 + 1
clocks.
Figure 39
Read Operation Followed by Precharge Example 1:
RL = 4 (AL = 1, CL = 3), BL = 4,
t
RTP
≤
2 clocks
Table 13
A10
LOW
LOW
LOW
LOW
HIGH
Bank Selection for Precharge by Address Bits
BA0
LOW
LOW
HIGH
HIGH
Don’t Care
BA1
LOW
HIGH
LOW
HIGH
Don’t Care
Precharge Bank(s)
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
all banks
NOP
Precharge
NOP
Bank A
Activate
NOP
NOP
READ A
Post CAS
T0
T2
T1
T3
T4
T5
T6
T7
T8
CMD
DQ
BR-P413
NOP
AL + BL/2 clks
Dout A0
Dout A1
Dout A2
Dout A3
AL = 1
CL = 3
RL = 4
>=tRAS
CL = 3
tRP
DQS,
DQS
NOP
>=tRC
>=tRTP
CK, CK
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