參數(shù)資料
型號(hào): HYB18T512800AC-5
廠商: INFINEON TECHNOLOGIES AG
英文描述: M39012 MIL RF CONNECTOR
中文描述: 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁(yè)數(shù): 46/96頁(yè)
文件大?。?/td> 2153K
代理商: HYB18T512800AC-5
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Data Sheet
46
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
Figure 36
Write Operation with Data Mask Example: RL = 3 (AL = 0, CL = 3), WL = 2,
t
WR
= 3, BL = 4
2.6.6
Interruption of a read or write burst is prohibited for
burst length of 4 and only allowed for burst length of 8
under the following conditions:
1. A Read Burst of 8 can only be interrupted by
another Read command. Read burst interruption by
a Write or Precharge Command is prohibited.
2. A Write Burst of 8 can only be interrupted by
another Write command. Write burst interruption by
a Read or Precharge Command is prohibited.
3. Read burst interrupt must occur exactly two clocks
after the previous Read command. Any other Read
burst interrupt timings are prohibited.
4. Write burst interrupt must occur exactly two clocks
after the previous Write command. Any other Read
burst interrupt timings are prohibited.
5. Read or Write burst interruption is allowed to any
bank inside the DDR2 SDRAM.
Burst Interruption
6. Read or Write burst with Auto-Precharge enabled is
not allowed to be interrupted.
7. Read burst interruption is allowed by a Read with
Auto-Precharge command.
8. Write burst interruption is allowed by a Write with
Auto-Precharge command.
9. All command timings are referenced to burst length
set in the mode register. They are not referenced to
the actual burst. For example, Minimum Read to
Precharge timing is AL + BL/2 where BL is the burst
length set in the mode register and not the actual
burst (which is shorter because of interrupt).
Minimum Write to Precharge timing is WL + BL/ 2 +
t
WR
, where
t
WR
starts with the rising clock after the
un-interrupted burst end and not form the end of the
actual burst end.
NOP
NOP
NOP
NOP
NOP
W RITE A
T0
T2
T1
T3
T4
T5
T6
T7
T9
WL = RL-1 = 2
DM
CMD
DQ
NOP
tW R
<= tDQSS
Precharge
Bank A
Activate
tRP
DQS,
DQS
DM
DIN A0 DIN A1
DIN A3
DIN A2
CK, CK
相關(guān)PDF資料
PDF描述
HYB18T512800AC DDR2 Registered Memory Modules
HYB18T512800AF DDR2 Registered Memory Modules
HYB18T512800AF-37 512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512800AF-5 512-Mbit Double-Data-Rate-Two SDRAM
HYB25D128160CE-5 128 Mbit Double Data Rate SDRAM
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