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參數(shù)資料
| 型號： | HYB18T512800AC-5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | M39012 MIL RF CONNECTOR |
| 中文描述： | 512兆雙數(shù)據(jù)速率2內(nèi)存 |
| 文件頁數(shù)： | 7/96頁 |
| 文件大小： | 2153K |
| 代理商： | HYB18T512800AC-5 |
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HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Overview
Data Sheet
7
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its
main characteristics.
1.1
Features
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
1.8 V
±
0.1 V Power Supply
1.8 V
±
0.1 V (SSTL_18) compatible I/O
DRAM organisations with 4, 8 and 16 data
in/outputs
Double Data Rate architecture: two data transfers
per clock cycle, four internal banks for concurrent
operation
CAS Latency: 3, 4 and 5
Burst Length: 4 and 8
Differential clock inputs (CK and CK)
Bi-directional, differential data strobes (DQS and
DQS) are transmitted / received with data. Edge
aligned with read data and center-aligned with write
data.
DLL aligns DQ and DQS transitions with clock
DQS can be disabled for single-ended data strobe
operation
Commands entered on each positive clock edge,
data and data mask are referenced to both edges of
DQS
Data masks (DM) for write data
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver impedance adjustment (OCD) and
On-Die-Termination (ODT) for better signal quality.
Auto-Precharge operation for read and write bursts
Auto-Refresh, Self-Refresh and power saving
Power-Down modes
Average Refresh Period 7.8
μ
s at a
T
CASE
lower
than 85 °C, 3.9
μ
s between 85 °C and 95 °C
Normal and Weak Strength Data-Output Drivers
1K page size for
×
4 &
×
8, 2K page size for
×
16
Packages:
P-TFBGA-60-6 for
×
4 &
×
8 components
P-TFBGA-84-1 for
×
16 components
1.2
Description
The 512-Mb DDR2 DRAM is a high-speed Double-
Data-Rate-2 CMOS Synchronous DRAM device
containing 536,870,912 bits and internally configured
as a quad-bank DRAM. The 512-Mb device is
organized as either 32 Mbit
×
4 I/O
×
4 bank, 16 Mbit
×
8 I/O
×
4 bank or 8 Mbit
×
16 I/O
×
4 bank chip. These
synchronous devices achieve high speed transfer rates
starting at 400 Mb/sec/pin for general applications. See
Table 1
for performance figures.
The device is designed to comply with all DDR2 DRAM
key features:
1. posted CAS with additive latency,
2. write latency = read latency - 1,
3. normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment and
5. an On-Die Termination (ODT) function.
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential
clocks (CK rising and CK falling). All I/Os are
synchronized with a single ended DQS or differential
DQS-DQS pair in a source synchronous fashion.
Table 1
Product Type Speed Code
Speed Grade
max. Clock Frequency
High Performance
–3.7
DDR2–533 4–4–4
266
266
200
15
15
45
60
–5
DDR2–400 3–3–3
200
200
200
15
15
40
55
Units
—
MHz
MHz
MHz
ns
ns
ns
ns
@CL5
@CL4
@CL3
f
CK5
f
CK4
f
CK3
t
RCD
t
RP
t
RAS
t
RC
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
相關PDF資料 |
PDF描述 |
|---|---|
| HYB18T512800AC | DDR2 Registered Memory Modules |
| HYB18T512800AF | DDR2 Registered Memory Modules |
| HYB18T512800AF-37 | 512-Mbit Double-Data-Rate-Two SDRAM |
| HYB18T512800AF-5 | 512-Mbit Double-Data-Rate-Two SDRAM |
| HYB25D128160CE-5 | 128 Mbit Double Data Rate SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYB18T512800AF-3S | 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84 |
| HYB18T512800BF-2.5 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T512800BF-3.7 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應商設備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF) |
| HYB18T512800BF-3S | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:2,500 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（單線） 電源電壓:1.8 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-MSOP 包裝:帶卷 (TR) |
| HYB25D128160AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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