參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 94/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
94
Datasheet
3.7.21.
BCTRL—PCI-PCI Bridge Control Register (Device 1)
Address Offset:
3Eh
Default:
00h
Access:
Read/Write
Size
8 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The
BCTRL provides additional control for the secondary interface (PCI1/AGP) as well as some bits that
affect the overall behavior of the “virtual” PCI-PCI bridge embedded within GMCH2-M, e.g. VGA
compatible address ranges mapping.
7
6
5
4
3
2
1
0
FB2B EN
(HW=0)
Sec Bus
Reset
(HW=0)
Master
Abort
Mode
(HW=0)
Reserved
VGA EN
ISA
Enable
SERR#
EN
(HW=0)
Parity Err
Response
EN
Bit
Descriptions
7
Fast Back to Back Enable.
Since there is only one target allowed on AGP this bit is meaningless.
This bit is
hardwired to “0”.
6
Secondary Bus Reset:
GMCH2-M does not support generation of reset via this bit on the AGP and
therefore this bit is
hardwired to “0”.
Note that the only way to perform a hard reset of the AGP is via the system reset either initiated
by software or hardware via ICH.
5
Master Abort Mode:
This bit is
hardwired to “0”.
This means when acting as a master on AGP/PCI1
the GMCH2-M will drop writes on the “floor” and return all “1” during reads when a Master Abort occurs.
4
Reserved.
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