參數(shù)資料
型號(hào)： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 52/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
52
Datasheet
3.6.15.
APCONT—Aperture Control (Device 0)
Address Offset:
51h
Default Value:
00h
Access:
Read/Write, Write Once, Read Only
Size:
8 bits
The Aperture Control Register controls selection and access to aperture space.
7
3
2
1
0
Reserved
AGP
Select
Lock
Aperture
Access
Global EN
AGP
Select
Bit
Description
7:3
Reserved
2
GFX AGP Select Lock (WO).
This GFX AGP Select (bit 0) can be made read only by this bit. This
is a write once bit, after it is written to it cannot be changed without a system reset.
0 = GFX AGP Select remains writeable.
1 = GFX AGP Select is read only.
1
Aperture Access Global Enable (Read/Write).
This bit is used to prevent access to the aperture
from any port (processor, PCI0 or AGP/PCI1) before the aperture range is established by the
configuration software and appropriate translation table in the main DRAM has been initialized.
Default is “0”
. It must be set after system is fully configured for aperture accesses.
0
GFX AGP Select. Read/Write, RO if GFX AGP Select Lock (bit 2 =1)
This field selects the
graphics device to be either AGP or Internal Graphics (GFX).
0 = AGP Mode. AGP interface device is enabled. All registers in device 0 and device 1 are visible.
No device 2 registers are visible, reads from those addresses will return 1’s.
1 = GFX Mode. Internal Graphics device is enabled. All non-AGP related device 0 registers and all
device 2 registers are visible. No device 1 registers are visible, reads from those addresses will
return 1’s. Reads from AGP related device 0 registers will return 0’s. The internal graphics device will
not respond to any configuration cycles unless SMRAM[7:6] @ 70h are NOT 00 AND APCONT[0] @
is 1.
GFX AGP Select
must be programmed before any other access is made to the configuration space.
The two possible modes are mutually exclusive. This bit determines whether other configuration
registers are enabled or disabled.This bit must be set as part of the initialization sequence.
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