參數(shù)資料
型號(hào)： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 126/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
126
Datasheet
Transaction
REQa[4:0]#
REQb[4:0]#
GMCH2-M Support
Memory Code
Read
0 0 1 0 0
0 0 x LEN#
Memory code read cycles are forwarded to DRAM or hub
interface.
Memory Data
Read
0 0 1 1 0
0 0 x LEN#
Host initiated memory read cycles are forwarded to DRAM
or the hub interface.
Memory Write
(no retry)
0 0 1 0 1
0 0 x LEN#
This memory write is a writeback cycle and cannot be
retried. The GMCH2-M will forward the write to DRAM.
Memory Write
(can be retried)
0 0 1 1 1
0 0 x LEN#
The standard memory write cycle will be forwarded to
DRAM or hub interface.
For Memory cycles, REQa[4:3]# = ASZ#. GMCH2-M only supports ASZ# = 00 (32 bit address).
REQb[4:3]# = DSZ#. DSZ# = 00 (64 bit data bus size).
LEN# = data transfer length as follows:
LEN#
00
01
10
11
Data length
<= 8 bytes (BE[7:0]# specify granularity)
Length = 16 bytes BE[7:0]# all active
Length = 32 bytes BE[7:0]# all active
Reserved
Table 13. Host Responses Supported by the GMCH2-M
RS2#
RS1#
RS0#
Description
GMCH2-M Support
0
0
0
idle
0
0
1
Retry
Response
This response is generated if an access is to a resource that
cannot be accessed by the processor at this time and the logic
must avoid deadlock. Hub interface directed reads, writes, and
DRAM locked reads can be retried.
0
1
0
Deferred
Response
This response can be returned for all transactions that can be
executed ‘out of order.’ Hub interface directed reads (memory,
I/O and Interrupt Acknowledge) and writes (I/O only), and
internal Graphics device directed reads (memory and I/O) and
writes (I/O only) can be deferred.
0
1
1
Reserved
Reserved
1
0
0
Hard Failure
Not supported.
1
0
1
No Data
Response
This is for transactions where the data has already been
transferred or for transactions where no data is transferred.
Writes and zero length reads receive this response.
1
1
0
Implicit
Writeback
This response is given for those transactions where the initial
transactions snoop hits on a modified cache line.
1
1
1
Normal Data
Response
This response is for transactions where data accompanies the
response phase. Reads receive this response.
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