參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 10/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
10
Datasheet
Intel
82815EM GMCH2-M Features
Processor/Host Bus Support
Optimized for the mobile Intel
Pentium
III
processor
and mobile Intel
Celeron processors.
Supports 32-Bit System Bus Addressing
4 deep in-order queue; 4 or 1 deep request queue
Supports Uni-processor systems only
In-order and Dynamic Deferred Transaction Support
100MHz System Bus Frequency
GTL+ I/O Buffer
Integrated SDRAM Controller
32 to 512MB using 16/64/128/256 Mbit technology
Supports up to 3 double sided SO-DIMMs @ 100Mhz
64-bit data interface
100MHz system memory bus frequency
Support for Asymmetrical SDRAM addressing only
Support for x8 and x16 SDRAM device width
Unbuffered, Non-ECC SDRAM only supported
Refresh Mechanism: CBR supported
Enhanced Open page Arbitration SDRAM paging scheme
Suspend to RAM support
Accelerated Graphics Port (AGP) Interface
Multiplexed with Internal Graphics
Supports a
single
AGP device
Supports AGP 2.0 including 4x AGP data transfers
AGP 2.0 support via dual mode buffers to allow 3.3v or
1.5v signaling
AGP PIPE# or SBA initiated accesses to SDRAM are
not
snooped
AGP FRAME# initiated accesses to SDRAM are snooped
High priority access support
Hierarchical PCI configuration mechanism
Delayed transaction support for AGP-to-SDRAM reads
that can not be serviced immediately
Arbitration Scheme and Concurrency
Intelligent Centralized Arbitration Model for Optimum
Concurrency Support
Concurrent operations of processor and System busses
supported via dedicated arbitration and data buffering
Data Buffering
Distributed Data Buffering Model for optimum
concurrency
SDRAM Write Buffer with read-around-write capability
Dedicated processor-SDRAM, hub interface-SDRAM and
Graphics-SDRAM Read Buffers
Power Management Functions
SMRAM space remapping to A0000h (128 KB)
Optional Extended SMRAM space above 256 MB,
additional 512K/1MB TSEG from Top of Memory,
cacheable
Stop Clock Grant and Halt special cycle translation from
the host to the hub interface
ACPI Compliant power management
Dynamic (independent) SCKE support
AGPBUSY# support
APIC Buffer Management
Integrated Graphics Controller Multiplexed with
AGP Controller
3D Hyper Pipelined Architecture
Parallel Data Processing (PDP)
Precise Pixel Interpolation (PPI)
Full 2D H/W Acceleration
Motion Video Acceleration
3D Graphics Visual Enhancements
Flat & Gouraud Shading
Mip Maps with Trilinear and Anisotropic Filtering
Full Color Specular
Fogging Atmospheric Effects
Z Buffering
3D Pipe 2D Clipping
Backface Culling
3D Graphics Texturing Enhancements
Per Pixel Perspective Correction Texture Mapping
Texture Compositing
Texture Color Keying/Chroma Keying
Digital Video Output Port (DVO)
Support for an external TV encoder
Video Controller Hub (VCH) Interface
196 Pin mini-BGA package
Display
Integrated 24-bit 230MHz RAMDAC
Gamma Corrected Video
DDC2B Compliant
2D Graphics
Up to 1600x1200 in 8-bit Color at 75 Hz Refresh
Hardware Accelerated Functions
3 Operand Raster BitBLTs
64x64x3 Color Transparent Cursor
Hardware Cursor and Popup window support
Arithmetic Stretch Blitter Video
H/W Assisted Motion Compensation for MPEG2 Decode
H/W assisted DVD playback at 30fps
H/W Overlay Engine with Bilinear Filtering
Independent gamma correction, saturation, brightness &
contrast for overlay
Integrated Graphics Memory Controller
Intel D.V.M. Technology
Display Cache Interface
32-bit data interface
100/133MHz SDRAM interface
Support for 2 1Mx16, or 1 2Mx32 SDRAM
4MB max addressable
Supporting I/O Bridge
360 Pin eBGA I/O Controller Hub (ICH2-M)
Packaging/Power
544 BGA
1.8V core with 3.3V CMOS I/O
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