參數(shù)資料
型號: 82815EM
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 38/163頁
文件大?。?/td> 1049K
代理商: 82815EM
Intel
82815EM GMCH
R
38
Datasheet
Bit
Descriptions
15:11
Device Number.
This field selects one agent on the PCI bus selected by the Bus Number.
During a Type 1 Configuration cycle this field is mapped to AD[15:11].
During a Type 0 Configuration Cycle this field is decoded and one bit among AD[31:11] is driven to a
1.
The GMCH2-M is always Device Number 0 for the Host bridge (GMCH2-M) entity,
The AGP bridge entity is always Device Number 1 and,
The Internal Graphics Device entity is always Device number 2.
If the Bus Number is non-zero and matches the value programmed into the SECONDARY BUS
NUMBER Register a Type 0 PCI configuration cycle will be generated on the AGP bridge. The Device
Number field is decoded and the GMCH2-M asserts one and only one GADxx signal as an IDSEL.
GAD16 is asserted to access Device #0, GAD17 for Device #1, GAD18 for Device #2 and so forth up
to Device #15 which will assert AD31. All device numbers higher than 15 cause a type 0 configuration
access with no IDSEL asserted, which will result in a Master Abort reported in the GMCH2-M’s “virtual”
PCI-PCI bridge registers.
For Bus Numbers resulting in hub interface configuration cycles the GMCH2-M propagates the Device
Number field as A[15:11]. For Bus Numbers resulting in AGP bridge Type 1 Configuration cycles the
Device Number is propagated as GAD[15:11].
10:8
Function Number.
This field is mapped to AD[10:8] during PCIx configuration cycles. This allows the
configuration registers of a particular function in a multi-function device to be accessed. The GMCH2-
M only responds to configuration cycles with a function number of 000b; all other function number
values attempting access to the GMCH2-M (Device Number = 0, 1 or 2, Bus Number = 0) will generate
a master abort.
7:2
Register Number.
This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address Register. This field is mapped to AD[7:2]
during PCI configuration cycles.
1:0
Reserved.
3.3.2.
CONFIG_DATA
I/O Address:
Default Value:
Access:
Size:
Configuration Data Register
0CFCh
00000000h
Read/Write
32 bits
CONFIG_DATA is a 32 bit Read/Write window into configuration space. The portion of configuration
space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS.
Bit
Descriptions
31:0
Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1 any I/O reference that falls in
the CONFIG_DATA I/O space will be mapped to configuration space using the contents of
CONFIG_ADDRESS.
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