參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 21/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
21
Signal Name
Type
Description
HIT#
I/O
GTL+
Hit:
Indicates that a caching agent holds an unmodified version of the requested
line. Also driven in conjunction with HITM# by the target to extend the snoop
window.
HITM#
I/O
GTL+
Hit Modified:
Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line.
HITM# is also driven in conjunction with HIT# to extend the snoop window.
HLOCK#
I
GTL+
Host Lock:
All processor bus cycles sampled with the assertion of HLOCK# and
ADS#, until the negation of HLOCK# must be atomic (i.e. no Hub interface or
GMCH2-M graphics snoopable access to SDRAM is allowed when HLOCK# is
asserted by the processor).
HREQ [4:0]#
I/O
GTL+
Host Request Command:
Asserted during both clocks of request phase. In the
first clock, the signals define the transaction type to a level of detail that is sufficient
to begin a snoop request. In the second clock, the signals carry additional
information to define the complete transaction type. The transactions supported by
the GMCH2-M are defined in the Host Interface section of this document.
HTRDY#
I/O
GTL+
Host Target Ready:
Indicates that the target of the processor transaction is able to
enter the data transfer phase.
RS [2:0]#
I/O
GTL+
Response Signals:
Indicates type of response as shown below:
RS[2:0] Response type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by the GMCH2-M)
100 Hard Failure (not driven by the GMCH2-M)
101 No data response
110 Implicit Writeback
111 Normal data response
GTLREF[1:0]
I
GTL Reference:
Reference voltage input for the Host GTL+ interface. GTLREF is
2/3* VTT. VTT is nominally 1.5v.
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