參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 132/163頁
文件大小： 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
132
Datasheet
4.11. Display Cache Interface
The GMCH2-M Display Cache (DC) is a single channel 32 bit wide SDRAM interface. The GMCH2-M
handles the control and timing for the display cache. The display cache interface of the GMCH2-M
generates the LCS#, LDQM[7:0], LSCAS#, LSRAS#, LWE#, LMD[31:0] and multiplexed addresses,
LMA[11:0] for the display cache DRAM array. The GMCH2-M also generates the clock LTCLK[1:0]
for write cycles as well as LOCLK for read cycle timings.
The display cache interface of the GMCH2-M supports single data rate synchronous dynamic random
access memory (SDRAM). It supports a single 32-bit wide memory channel. The interface handles the
operation of D.V.M. with DC at 100/133MHz. The DRAM controller interface is fully configurable
through a set of control registers.
Internal buffering (FIFOs) of the data to and from the display cache ensures the synchronization of the
data to the internal pipelines. The D.V.M. with DC interface clocking is divided synchronous with
respect to the core and system bus.
The startup sequencing for the local memory display cache, is as follows:
System BIOS detects if an external AGP device is present by doing a config read to PCI. If an AGP
device is present, it becomes the display device and bit 0 of the APCONT register should be set to
0. No further initialization of internal graphics will take place. If internal graphics is the preferred
display device, bit 0 of the APCONT register should be set to 1. If no AGP device is present, the
internal graphics becomes the display device and bit 0 of the APCONT register should be set to 1.
PCI enumeration takes place at this point.
In the case where internal graphics is selected, the remaining steps still apply:
System BIOS determines if local memory display cache is present. If present the following steps
take place:
Local Memory Clock Frequency is determined with a reset strap (on AGP pin SBA[7])
sampled as an input during reset.
Memory Timing Options will be determined empirically by the system BIOS. The BIOS will
start with programming slow timings (CAS Latency, RAS Pre-charge, etc.) and then trying
faster timings until it breaks. The settings, which optimize performance without compromising
functionality, will be selected.
4.11.1.
Supported DRAM Types for Display Cache Memory
1Mx16 and 2Mx32 SDRAMs are supported, but the maximum memory supported is 4MB of display
cache memory.
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