參數(shù)資料
型號(hào)： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 70/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
70
Datasheet
3.6.28.
AGPSTAT—AGP Status Register (Device 0)
Address Offset:
A4-A7h
Default Value:
1F000207h
Access:
Read Only
Size:
32 bits
This register reports AGP device capability/status.
(AGP MODE ONLY)
31
24
Request Queue (RQ) (HW=1Fh)
23
16
Reserved
15
10
9
8
Reserved
SBA
(HW=1)
Reserved
7
6
5
4
3
2
0
Reserved
>4 GB
Support
(HW=0)
Fast
Writes
(HW=0)
Reserved
Data Transfer Rate
(HW=111)
Bit
Description
31:24
RQ.
This field contains the maximum number of AGP command requests the GMCH2-M is configured
to manage. The lower 6 bits of this field reflect the value programmed in AGPCTRL[12:10]. Only
discrete values of 32, 16, 8, 4 , 2 and 1 can be selected via AGPCTRL.
Upper bits are hardwired to “0”. Default =1Fh to allow a maximum of 32 outstanding AGP command
requests.
23:10
Reserved
9
SBA.
This bit indicates that the GMCH2-M supports side band addressing. It is hardwired to 1.
8:6
Reserved
5
4G.
This bit indicate that the GMCH2-M does
not
support addresses greater than 4 gigabytes. It is
hardwired to 0.
4
FW.
This bit indicate that the GMCH2-M does
not
support fast writes from the processor-to-AGP
master. It is hardwired to 0.
3
Reserved
2:0
Rat
e. After reset the GMCH2-M reports its data transfer rate capability.
Default Value = 111.
Note that the selected data transfer mode applies to both AD bus and SBA bus.
Bit 0 (high) = AGP device supports 1x data transfer mode
Bit 1 (high) = AGP device supports 2x data transfer mode
Bit 2 (high) = AGP device supports 4x data transfer mode. This bit can be masked by the AGPCTRL
register bit 0 (See PCI Configuration Space Table 3-1).
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