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| 型號(hào)： | 82815EM |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 127/163頁 |
| 文件大?。?/td> | 1049K |
| 代理商： | 82815EM |
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Intel
82815EM GMCH
R
Datasheet
127
4.8.2.
Special Cycles
A Special Cycle is defined when REQa [4:0] = 01000 and REQb [4:0]= xx001. The first address phase
Aa [35:3]# is undefined and can be driven to any value. The second address phase, Ab [15:8]# defines
the type of Special Cycle issued by the processor.
The following table specifies the cycle type and definition, as well as the action taken by the GMCH2-M
when the corresponding cycles are identified.
Table 14. Special Cycles
BE[7:0}#
Special Cycle Type
Action Taken
0000 0000
NOP
This transaction has no side-effects.
0000 0001
Shutdown
This transaction is issued when an agent detects a severe software error
that prevents further processing. This cycle is claimed by the GMCH2-M.
The GMCH2-M issues a shutdown special cycle on the hub interface.
This cycle is retried on the processor bus after it is terminated on the hub
interface via a master abort mechanism.
0000 0010
Flush
This transaction is issued when an agent has invalidated its internal
caches without writing back any modified lines. The GMCH2-M claims
this cycle and retries it.
0000 0011
Halt
This transaction is issued when an agent executes a HLT instruction and
stops program execution. This cycle is claimed by the GMCH2-M and
propagated to the hub interface as a Special Halt Cycle. This cycle is
retried on the processor bus after it is terminated on the hub interface via
a master abort mechanism.
0000 0100
Sync
This transaction is issued when an agent has written back all modified
lines and has invalidated its internal caches. The GMCH2-M claims this
cycle and retries it.
0000 0101
Flush Acknowledge
This transaction is issued when an agent has completed a cache sync
and flush operation in response to an earlier FLUSH# signal assertion.
The GMCH2-M claims this cycle and retires it.
0000 0110
Stop Clock
Acknowledge
This transaction is issued when an agent enters Stop Clock mode. This
cycle is claimed by the GMCH2-M and propagated to the hub interface as
a Special Stop Grant Cycle. This cycle is completed on the processor
bus after it is terminated on the hub interface via a master abort
mechanism.
0000 0111
SMI Acknowledge
This transaction is first issued when an agent enters the System
Management Mode (SMM). Ab[7]# is also set at this entry point. All
subsequent transactions from the processor with Ab[7]# set are treated
by the GMCH2-M as accesses to the SMM space. No corresponding
cycle is propagated to the hub interface. To exit the System Management
Mode the processor issues another one of these cycles with the Ab[7]#
bit deasserted. The SMM space access is closed by the GMCH2-M at
this point.
all others
Reserved
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