參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 84/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
84
Datasheet
3.7.7.
BCC1—Base Class Code Register (Device 1)
Address Offset:
0Bh
Default Value:
06h
Access:
Read Only
Size:
8 bits
This register contains the Base Class Code of the GMCH2-M Device 1. This code is 06h indicating a
Bridge device. This register is read only.
Bit
Description
7:0
Base Class Code (BASEC)
. This is an 8-bit value that indicates the Base Class Code for the GMCH2-
M Device 1. This code has the value 06h, indicating a Bridge device.
3.7.8.
MLT1—Master Latency Timer Register (Device 1)
Address Offset:
0Dh
Default Value:
00h
Access:
Read/Write
Size:
8 bits
This functionality is not applicable. It is described here since these bits should be implemented as a
Read/Write to prevent standard PCI-PCI bridge configuration software from getting “confused”.
7
6
5
4
3
2
0
Not Applicable
Reserved
Bit
Description
7:3
Not applicable but support Read/Write operations.
(Reads return previously written data.)
2:0
Reserved.
3.7.9.
HDR1—Header Type Register (Device 1)
Address Offset:
0Eh
Default:
01h
Access:
Read Only
Size:
8 bits
This register identifies the header layout of the configuration space. No physical register exists at this
location.
Bit
Descriptions
7:0
This read only field always returns 01h when read. Writes have no effect.
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