參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 115/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
Datasheet
115
Memory
Segments
Attributes
Comments
0F0000H -
0FFFFFH
WE RE
BIOS Area
4.2.1.1.
DOS Area (00000h-9FFFh)
The DOS area is 640 KB in size is always mapped to the main memory controlled by the GMCH2-M.
4.2.1.2.
Video Buffer Area (A0000h-BFFFFh)
The 128KB graphics adapter memory region is normally mapped to a legacy video device on the PCI bus
(typically VGA controller). This memory area is not controlled by attribute bits of the PAM register.
processor-initiated cycles in this region are forwarded to the hub interface or the AGP/Internal Graphics
Device for termination. Accesses to this range are directed to either the hub interface or AGP/internal
Graphics Device based on the configuration. The configuration are specified by:
AGP on/off configuration bit
AGP off: GMS bits of the SMRAM register in the GMCH2-M Device #0 configuration space.
There is additional steering information coming from the Device #2* configuration registers and
from some of the VGA registers in the Graphics device.
AGP on: PCICMD1 (PCI-PCI Command) and BCTRL (PCI-PCI Bridge Control) registers in
Device #1 configuration registers
The control is applied for accesses initiated from any of the system interface i.e. processor bus, the hub
interface, or AGP (if enabled).
For Hub interface to AGP/PCI bus accesses, only memory write operations are supported. Any AGP/PCI
initiated VGA accesses targeting the GMCH2-M will master abort.
This region is also the default region for SMM space in GFX mode. The SMRAM Control register
controls how SMM accesses to this space are treated.
4.2.1.3.
Monochrome Adapter (MDA) Range (B0000h - B7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome) in the system.
In an AGP system, accesses in the standard VGA range are forwarded to the AGP bus (depending on
configuration bits). Since the monochrome adapter may be on the hub interface/PCI (or ISA) bus,
GMCH2-M must decode cycles in the MDA range and forward them to the hub interface. This
capability is controlled by a configuration bit (MDA bit – Device 0, BEh). In addition to the memory
range B0000h to B7FFFh, the GMCH2-M decodes IO cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and
3BFh and forwards them to the hub interface bus
In an internal graphics system, the GMS bits of the SMRAM register in Device #0, bits in the Device #2
PCICMD2 register and bits from some of the VGA registers control this functionality.
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