參數(shù)資料
型號(hào): 82815EM
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù): 125/163頁(yè)
文件大?。?/td> 1049K
代理商: 82815EM
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Intel
82815EM GMCH
R
Datasheet
125
4.8.
Host Interface
The host interface of the GMCH2-M is optimized to support the mobile Intel
Pentium
III
processor,
Intel
Pentium
II processor, and Intel
Celeron
processor. The GMCH2-M implements the host
address, control, and data bus interfaces within a single device. The GMCH2-M supports a 4-deep in-
order queue (i.e., supports pipelining of up to 4 outstanding transaction requests on the host bus). Host
bus addresses are decoded by the GMCH2-M for accesses to system memory, PCI memory & PCI I/O
(via hub interface), PCI configuration space and Graphics memory. The GMCH2-M takes advantage of
the pipelined addressing capability of the processor to improve the overall system performance.
4.8.1.
Host Bus Device Support
The GMCH2-M supports a large subset of the transaction types that are defined for the Intel
Pentium
III
processor, Intel
Pentium
II processor, or Intel
Celeron
processor bus interface. However, each of
these transaction types has a multitude of response types, some of which are not supported by this
controller. All transactions are processed in the order that they are received on the processor bus.
Table 12. Summay of Transactions Supported By GMCH2-M
Transaction
REQa[4:0]#
REQb[4:0]#
GMCH2-M Support
Deferred Reply
0 0 0 0 0
X X X X X
The GMCH2-M will initiate a deferred reply request for a
previously deferred transaction.
Reserved
0 0 0 0 1
X X X X X
Reserved
Interrupt
Acknowledge
0 1 0 0 0
0 0 0 0 0
Interrupt acknowledge cycles are forwarded to the hub
interface.
Special
Transactions
0 1 0 0 0
0 0 0 0 1
See separate table in special cycles section.
Reserved
0 1 0 0 0
0 0 0 1 x
Reserved
Reserved
0 1 0 0 0
0 0 1 x x
Reserved
Branch Trace
Message
0 1 0 0 1
0 0 0 0 0
The GMCH2-M will terminate a branch trace message
without latching data.
Reserved
0 1 0 0 1
0 0 0 0 1
Reserved
Reserved
0 1 0 0 1
0 0 0 1 x
Reserved
Reserved
0 1 0 0 1
0 0 1 x x
Reserved
I/O Read
1 0 0 0 0
0 0 x LEN#
I/O read cycles are forwarded to hub interface. I/O cycles
which are in the GMCH2-M configuration space will not be
forwarded to the hub interface.
I/O Write
1 0 0 0 1
0 0 x LEN#
I/O write cycles are forwarded to hub interface. I/O cycles
which are in the GMCH2-M configuration space will not be
forwarded to hub interface.
Reserved
1 1 0 0 x
0 0 x x x
Reserved
Memory Read &
Invalidate
0 0 0 1 0
0 0 x LEN#
Host initiated memory read cycles are forwarded to DRAM
or the hub interface.
Reserved
0 0 0 1 1
0 0 x LEN#
Reserved
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