參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 40/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
40
Datasheet
3.5.1.
Logical PCI Bus #0 Configuration Mechanism
The GMCH2-M decodes the Bus Number (bits 23:16) and the Device Number fields of the CONFIG_
ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the configuration cycle is
targeting a PCI Bus #0 device.
Device #0
: The Host-hub Bridge/DRAM Controller entity is hardwired as Device #0 on PCI Bus #0.
Device #1
: The AGP interface entity is hardwired as Device #1 on PCI Bus #0.
Device #2
: The internal graphics device (GFX) entity is hardwired as Device #2 on PCI Bus #0.
Configuration cycles to one of the GMCH2-M internal devices are confined to the GMCH2-M and not
sent over the Hub interface. Accesses to devices #3 to #31 on PCI Bus #0 will be forwarded over the
Hub interface.
3.5.2.
Primary PCI (PCI0) and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero the GMCH2-M will generate a configuration
cycle over the hub interface. The ICH2-M compares the non-zero Bus Number with the SECONDARY
BUS NUMBER and SUBORDINATE BUS NUMBER registers of its P2P bridges to determine if the
configuration cycle is meant for Primary PCI expansion bus (PCI0), or a downstream PCI bus.
3.5.3.
Internal Graphics Device (GFX) Configuration Mechanism
From the chipset configuration perspective the internal graphics device is seen as a PCI device (device
#2) on PCI Bus #0. Configuration cycles that target device #2 on PCI Bus #0 will be claimed by the
internal graphics device and will not be forwarded via hub interface to the ICH2-M.
3.6.
Host-Hub Interface Bridge/DRAM Controller Device
Registers (Device #0)
Device #0 registers come in two categories
Those visible in both
GFX mode
and
AGP mode
.
Those visible only in
AGP mode
. These are always appended with the message
AGP Mode Only
.
When GMCH2-M is in internal graphics (GFX) mode most of the configuration bits needed to configure
Device #0 are needed in AGP mode as well. The few exceptions are don’t care situations in AGP. In
AGP mode, a number of bits to control the AGP port are made visible only in AGP mode. They will
read back 0s in GFX mode. The following table shows the GMCH2-M configuration space for device
#0.
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