參數(shù)資料
型號(hào)： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 130/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
130
Datasheet
4.9.2.
DRAM Address Translation and Decoding
The GMCH2-M contains address decoders that translate the address received on the host bus, hub
interface, or from the internal Graphics device to an effective memory address. The GMCH2-M supports
16 and 64 Mbit SDRAM devices. The GMCH2-M supports a 2 KB page sizes only. The multiplexed row
/ column address to the DRAM memory array is provided by the SBS[1:0] and SMAA[11:0] signals and
copies. These addresses are derived from the host address bus as defined by the following table for
SDRAM devices. Row size is internally computed using the values programmed in the DRP register.
Up to 4 pages can be open at any time within any row (Only 2 active pages are supported in rows
populated with either 8 MBs or 16 MBs).
Table 16. GMCH2-M DRAM Address Mux Function
Address Usage
B
B
M
M
M
M
M
M
M
M
M
M
M
M
M
Tech
(Mb)
D
W
Row
Col
Bank
MemS
ize
(MB)
1
0
12
11
10
9
8
7
6
5
4
3
2
1
0
16
2M
8
11
9
1
16
X
11
X
X
[A]
22
21
20
19
18
17
16
15
14
13
X
11
X
X
PA
X
23
10
9
8
7
6
5
4
3
64
8M
8
12
9
2
64
12
11
X
24
[A]
22
21
20
19
18
17
16
15
14
13
12
11
X
X
PA
X
25
10
9
8
7
6
5
4
3
64
4M
16
12
8
2
32
12
11
X
24
[A]
22
21
20
19
18
17
16
15
14
13
12
11
X
X
PA
X
X
10
9
8
7
6
5
4
3
128
16M
8
12
10
2
128
12
11
X
24
[A]
22
21
20
19
18
17
16
15
14
13
12
11
X
X
PA
26
25
10
9
8
7
6
5
4
3
128
8M
16
12
9
2
64
12
11
X
24
[A]
22
21
20
19
18
17
16
15
14
13
12
11
X
X
PA
X
25
10
9
8
7
6
5
4
3
256
32M
8
13
10
2
256
12
11
27
24
[A]
22
21
20
19
18
17
16
15
14
13
12
11
X
X
PA
26
25
10
9
8
7
6
5
4
3
256
16M
16
13
9
2
128
12
11
26
24
[A]
22
21
20
19
18
17
16
15
14
13
12
11
X
X
PA
X
25
10
9
8
7
6
5
4
3
NOTES:
MA bit 10 at RAS time uses the XOR of Address bit 12 and Address bit 23
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