參數(shù)資料
型號： 82815EM
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 44/163頁
文件大?。?/td> 1049K
代理商： 82815EM
Intel
82815EM GMCH
R
44
Datasheet
3.6.3.
PCICMD—PCI Command Register (Device 0)
Address Offset:
04-05h
Default:
0006h
Access:
Read/Write
Size:
16 bits
The PCICMD Register enables and disables the SERR# signal.
15
10
9
8
Reserved (0)
(HW=0)
SERR En
7
6
5
4
3
2
1
0
(HW=0)
(HW=0)
(HW=0)
(HW=0)
(HW=0)
(HW=1)
(HW=1)
(HW=0)
Bit
Descriptions
15:10
Reserved
.
9
Fast Back-to-Back.
Not implemented by GMCH2-M; hardwired to 0.
8
SERR Enable (SERRE)
. This bit is a global enable bit for Device 0 SERR messaging. The GMCH2-M does not have an
SERR# signal. The GMCH2-M communicates the SERR# condition by sending an SERR message to the ICH. If this bit
is set to a 1, the GMCH2-M is enabled to generate SERR messages over the Hub interface for specific Device 0 error
conditions If SERRE is reset to 0, then the SERR message is not generated by the GMCH2-M for Device 0.
NOTE: This bit only controls SERR messaging for the Device 0. Device 1 has its own SERRE bit to control error
reporting for error conditions occurring on Device 1. The two control bits are used in a logical OR manner to
enable the SERR hub interface message mechanism.
7
Address/Data Stepping.
Not implemented by GMCH2-M; hardwired to 0
6
Parity Error Enable (PERRE).
Not implemented by GMCH2-M;hardwired to 0. Writes to this bit position have no affect.
5
VGA Palette Snoop.
Not implemented by GMCH2-M; hardwired to 0. Writes to this bit position have no affect.
4
Memory Write and Invalidate Enable.
Not implemented, is hardwired to 0. Writes to this bit position have no affects.
3
Special Cycle Enable.
(Not implemented by GMCH2-M; hardwired to 0).
GMCH2-M ignores all special cycles
generated on the PCI.
2
Bus Master Enable (BME)
.
(Not implemented by GMCH2-M; hardwired to 1).
GMCH2-M is always allowed to be a
Bus Master. . Writes to this bit position have no affect.
1
Memory Access Enable (MAE)
.
(Not implemented by GMCH2-M; hardwired to 1).
GMCH2-M always allows access
to main memory. Writes to this bit position have no affect.
0
I/O Access Enable (IOAE)
.
(Not implemented; hardwired to 0).
Writes to this bit position have no affect.
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